XRT86VL38_1 Datasheet, PDF (44/66 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
REV. V1.2.0
420 PKG 484PKG
SIGNAL NAME
BALL# BALL #
REQ1
AA24
Y22
TYPE
O
OUTPUT
DRIVE (MA)
DESCRIPTION
8
DMA Cycle Request Output—DMA Controller 1 (Read):
These output pins are used to indicate that DMA transfers
(Read) are requested by the T1/E1 Framer.
On the receive side (i.e., To transmit data from HDLC buff-
ers within the XRT86VL38 to external DMA Controller),
DMA transfers are only requested when the receive buffer
contains a complete message or cell.
The DMA Read cycle starts by T1/E1 Framer asserting the
DMA Request (REQ1) ‘low’, then the external DMA control-
ler should drive the DMA Acknowledge (ACK1) ‘low’ to indi-
cate that it is ready to receive the data. The T1/E1 Framer
should place new data on the Microprocessor data bus
each time the Read Signal is Strobed low if the RD is con-
figured as a Read Strobe. If RD is configured as a direction
signal, then the T1/E1 Framer would place new data on the
Microprocessor data bus each time the Write Signal (WR)
is Strobed low.
The Framer asserts this output pin (toggles it "Low") when
one of the Receive HDLC buffer contains a complete
HDLC message that needs to be read by the µC/µP.
The Framer negates this output pin (toggles it “High”) when
the Receive HDLC buffers are depleted.
INT
R26
N22
O
8
Interrupt Request Output:
This active-low output signal will be asserted when the
XRT86VL38 device is requesting interrupt service from the
Microprocessor. This output pin should typically be con-
nected to the “Interrupt Request” input of the Microproces-
sor.
The Framer will assert this active "Low" output (toggles it
"Low"), to the local µP, anytime it requires interrupt service.
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