XR16V798 Datasheet, PDF (41/56 Pages) Exar Corporation – HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE

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XR16V798
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
FCTR[4]: Infrared RX Input Logic Select
• Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default).
• Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is
selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger
level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control.
Table 17 shows the 16 selectable hysteresis levels.
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT-3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FCTR BIT-2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
FCTR BIT-1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FCTR BIT-0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RTS/DTR HYSTERESIS
(CHARACTERS)
0
+/- 4
+/- 6
+/- 8
+/- 8
+/- 16
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
4.13 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bits 3:0 provide single or dual consecutive
character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
• Logic 0 = Automatic CTS/DSR flow control is disabled (default).
• Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts
(HIGH). Transmission resumes when CTS/DSR# pin is asserted (LOW). The selection for CTS# or DSR# is
through MCR bit-2.
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