XR16C2850_05 Datasheet, PDF (40/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
xr
REV. 2.1.3
AC ELECTRICAL CHARACTERISTICS
TA=0^O TO 70^OC (-40^O TO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.90V TO 5.5V, 70 PF LOAD
WHERE APPLICABLE
SYMBOL
PARAMETER
CLK Clock Pulse Duration
LIMITS
3.3
MIN
MAX
LIMITS
5.0
MIN
MAX
30
20
UNIT
ns
CONDITIONS
OSC Oscillator Frequency
8
24 MHz
OSC External Clock Frequency
33
50 MHz
TAS Address Setup Time
5
0
ns
TAH Address Hold Time
10
5
ns
(top mark date code of "DC YYWW" and older)
TAH Address Hold Time
0
(top mark date code of "F2 YYWW" and newer)
0
ns
TCS Chip Select Width
66
50
ns
TRD IOR# Strobe Width
35
25
ns
TDY Read Cycle Delay
40
30
ns
TRDV
TDD
TWR
Data Access Time
Data Disable Time
IOW# Strobe Width
35
25
ns
0
25
0
15
ns
40
25
ns
TDY Write Cycle Delay
40
30
ns
TDS Data Setup Time
20
15
ns
TDH Data Hold Time
5
5
ns
TWDO Delay From IOW# To Output
50
40
ns 100 pF load
TMOD Delay To Set Interrupt From MODEM Input
TRSI Delay To Reset Interrupt From IOR#
TSSI Delay From Stop To Set Interrupt
TRRI Delay From IOR# To Reset Interrupt
40
35
ns 100 pF load
40
35
ns 100 pF load
1
1
Bclk
45
40
ns 100 pF load
TSI Delay From Stop To Interrupt
45
40
ns
TINT Delay From Initial INT Reset To Transmit Start
8
24
8
24 Bclk
TWRI Delay From IOW# To Reset Interrupt
45
40
ns
TSSR Delay From Stop To Set RXRDY#
1
1
Bclk
TRR Delay From IOR# To Reset RXRDY#
45
TWT Delay From IOW# To Set TXRDY#
45
TSRT Delay From Center of Start To Reset TXRDY#
8
40
ns
40
ns
8
Bclk
40