XRT73R12 Datasheet, PDF (4/87 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.3
PRELIMINARY
FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED).................................................................................... 29
FIGURE 18. B3ZS ENCODING FORMAT ................................................................................................................................................. 29
4.4 TRANSMIT PULSE SHAPER ......................................................................................................................... 30
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT.............................................................................................................................. 30
4.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................. 30
FIGURE 19. HDB3 ENCODING FORMAT ................................................................................................................................................. 30
4.5 E3 LINE SIDE PARAMETERS ........................................................................................................................ 31
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703 ............................................................................. 31
TABLE 4: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .............................................................. 32
FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ................................. 33
TABLE 5: STS-1 PULSE MASK EQUATIONS ........................................................................................................................................... 33
TABLE 6: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)..................................... 34
FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ......................................................................... 34
TABLE 8: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ........................................ 35
TABLE 7: DS3 PULSE MASK EQUATIONS............................................................................................................................................... 35
4.6 TRANSMIT DRIVE MONITOR ........................................................................................................................ 36
4.7 TRANSMITTER SECTION ON/OFF ............................................................................................................... 36
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP................................................................................................................................... 36
5.0 JITTER ..................................................................................................................................................37
5.1 JITTER TOLERANCE ..................................................................................................................................... 37
5.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS ................................................................................................ 37
FIGURE 25. JITTER TOLERANCE MEASUREMENTS .................................................................................................................................. 37
5.1.2 E3 JITTER TOLERANCE REQUIREMENTS .............................................................................................................. 38
FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1 ...................................................................................................................... 38
FIGURE 27. INPUT JITTER TOLERANCE FOR E3..................................................................................................................................... 38
5.2 JITTER TRANSFER ........................................................................................................................................ 39
TABLE 9: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ........................................................................... 39
TABLE 10: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................................................... 39
TABLE 11: JITTER TRANSFER PASS MASKS ........................................................................................................................................... 39
5.2.1 JITTER GENERATION................................................................................................................................................ 40
FIGURE 28. JITTER TRANSFER REQUIREMENTS ..................................................................................................................................... 40
6.0 DIAGNOSTIC FEATURES ...................................................................................................................41
6.1 PRBS GENERATOR AND DETECTOR ......................................................................................................... 41
FIGURE 29. PRBS MODE ................................................................................................................................................................... 41
6.2 LOOPBACKS .................................................................................................................................................. 42
6.2.1 ANALOG LOOPBACK ................................................................................................................................................ 42
FIGURE 30. ANALOG LOOPBACK ........................................................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ................................................................................................................................................. 43
6.2.3 REMOTE LOOPBACK ................................................................................................................................................ 43
FIGURE 31. DIGITAL LOOPBACK ............................................................................................................................................................ 43
FIGURE 32. REMOTE LOOPBACK ........................................................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) ...................................................................................................................... 44
FIGURE 33. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 44
7.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................45
TABLE 12: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 45
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 45
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 46
TABLE 13: XRT73R12 MICROPROCESSOR INTERFACE SIGNALS ............................................................................................................ 46
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 47
TABLE 14: ASYNCHRONOUS TIMING SPECIFICATIONS............................................................................................................................. 48
FIGURE 35. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................................. 48
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................................... 49
TABLE 15: SYNCHRONOUS TIMING SPECIFICATIONS............................................................................................................................... 49
7.3 REGISTER MAP ............................................................................................................................................. 50
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT73R12............................................................................................ 50
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................................ 59
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................................... 59
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS........................................................................................................ 59
TABLE 18: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ..................................................... 59
TABLE 19: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR8 (ADDRESS LOCATION = 0X08) ..................................................... 60
TABLE 20: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR96 (ADDRESS LOCATION = 0X60) ......................................................... 61
TABLE 21: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0)....................................................... 62
TABLE 22: THE ABOVE IS: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61) .................................. 63
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