XRK39653_0611 Datasheet, PDF (4/9 Pages) Exar Corporation – 3.3V, 8-OUTPUT ZERO DELAY BUFFER

XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
xr
REV. 1.0.0
DC CHARACTERISTICS (V_CC= 3.3 + 5%, T_A= -40°C TO +85°C)
SYMBOL
CHARACTERISTICS
V_CMRa ^{PECL Clock inputs common mode range}
V_PP PECL Clock peak-to-peak input voltage
V_IH Input voltage high
V_IL Input voltage low
V_{OH Output High Voltage}^a
V_{OL Output Low Voltage}^a
Z_OUT Output Impedance
I_IN
Input leakage current
I_{CC_PLL} Maximum PLL supply current
I_CCQ Maximum Quiescent supply current
V_TT Output Termination Voltage
MIN
TYP
MAX UNIT
CONDITION
1.0
V_DD-0.6 V LVPECL
300
1000 mV LVPECL
2.0
V_DD+0.3 V LVCMOS
0.8
V LVCMOS
2.4
V I_OH=-24mA
14-17
0.55
0.30
V I_OL=24mA
V _IOL=12mA
Ω
5.0
V_CC÷2
+200
10.0
10.0
μΑ V_IN =V_DD or V_IN =GND
mA AV_DD pin
mA All V_DD pins, OE=1
V
a. VCMR is the cross point of the differential input signal.
.
AC CHARACTERISTICS (V_CC= 3.3 + 5%, T_A= -40°C TO +85°C) ^a
SYMBOL
PARAMETER
MIN
f_VCO VCO Frequency
200
f_ref Input Reference Frequency
÷4 feedback 50
÷8 feedback 25
PLL Bypass
0
f_MAX Max Output Frequency
÷4 feedback 50
÷8 feedback 25
V_PP PECL Clock peak-to-peak input voltage
450
V_CMR PECL input Common Mode range
1.2
t_{PW Min} Input Reference Clock Minimum Pulse Width
2
t_SPO Propagation Delay - Static Phase Offset (PECL
-75
to FB_IN)
t_PD Propagation Delay - PLL Bypassed
Bypass mode 1 (BYPASS = 0)
1.2
Bypass mode 2, (BYPASS = 1, PLL_EN = 0)
3.0
t_skew(O) Output-to-Output Skew
t_skew(PP) Part to Part Skew (bypass PLL & divider)
t_JIT(CC) Cycle-to-Cycle Jitter
TYP
MAX
UNIT
CONDITION
500
MHz
125
62.5
200
125
62.5
1000
MHz
MHz
mV
PLL locked
PLL locked
bypass mode
PLL locked
PLL locked
LVPECL
V_DD-0.75
V
ns
LVPECL
125
ps
PLL locked
3.3
ns
7.0
ns
150
ps
1.5
ns
BYPASS=0
100
ps
4