XRA1403 Datasheet, PDF (4/16 Pages) Exar Corporation – 16-BIT SPI GPIO EXPANDER WITH RESET INPUT

XRA1403
16-BIT SPI GPIO EXPANDER WITH RESET INPUT
REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTION
1.1 SPI bus Interface
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 26 MHz. To access the device in the SPI
mode, the CS# signal is asserted by the SPI master, then the SPI master starts toggling the SCL signal with
the appropriate transaction information. The first bit sent by the SPI master includes whether it is a read or
write transaction and the register being accessed. See Table 1 below.
TABLE 1: SPI COMMAND BYTE FORMAT
BIT
FUNCTION
7 Read/Write#
Logic 1 = Read
Logic 0 = Write
6:1 Command Byte
0 Reserved
FIGURE 3. SPI WRITE
SCL
SI
0 0 0 A3 A2 A1 A0 X D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 4. SPI READ
SCL
SI
1 0 0 A3 A2 A1 A0 X
SO
D7 D6 D5 D4 D3 D2 D1 D0
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
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