XRA1200 Datasheet, PDF (4/16 Pages) Exar Corporation – 8-BIT I2C/SMBUS GPIO EXPANDER

XRA1200/1200P
8-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
1.1 I²C-bus Interface
The I²C-bus interface is compliant with the Standard-mode and Fast-mode I²C-bus specifications. The I²C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I²C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA120x responds to each write with an acknowledge
(SDA driven LOW by XRA1200/1200P for one clock cycle when SCL is HIGH). The last byte sent by an I²C-
bus master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5
below. For complete details, see the I²C-bus specifications.
FIGURE 3. I²C START AND STOP CONDITIONS
SDA
SCL
S
START condition
P
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE
S
SLAVE
ADDRESS
WA
COMMAND
BYTE
A
W hite block: host to XR A120x
G rey block: X R A 120x to host
DATA
BYTE
AP
FIGURE 5. MASTER READS FROM SLAVE
S
SLAVE
ADDRESS
WA
White block: host to XRA120x
Grey block: XRA120x to host
COMMAND
BYTE
AS
SLAVE
ADDRESS
RA
nDATA
A
LAST DATA NA P
4