XR19L202 Datasheet, PDF (4/50 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L202
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
Pin Descriptions
REV. 1.0.0
NAME
48-QFN
PIN#
TYPE
DESCRIPTION
MODEM OR SERIAL I/O INTERFACE (EIA-232/RS-232 Voltage Levels)
TXDA
33
O _{UART Channel A Transmit Data. The TX signal will be LOW (< 1.5V) during reset or idle (no}
data).
RXDA
27
I _{UART Channel A Receive Data. The RX data input must idle LOW (< 1.5V). This input has}
an internal pull-down resistor and can be left unconnected when not used.
TXDB
22
O _{UART Channel B Transmit Data. The TX signal will be LOW (< 1.5V) during reset or idle (no}
data).
RXDB
25
I _{UART Channel B Receive Data. RXDB will be the input signal to the internal UART when}
RXBSEL is LOW. If RXB is used, then RXBSEL should be HIGH. The RX data input must
idle LOW (< 1.5V). This input has an internal pull-down resistor and can be left uncon-
nected when not used.
SERIAL I/O INTERFACE (CMOS/TTL Voltage Levels)
TXB
9
O _{UART Channel B Transmit data. This is the TXB output signal from the UART. This pin can}
be used to communicate with an external Infrared or RS-422 transceiver if TXDB is unused.
RXB
8
I _{UART Channel B Receive data. This is the RXB input signal to the UART. If RXDB is not}
used (RXBSEL is HIGH), then this pin can be used to communicate with an external Infra-
red or RS-422 transceiver. If RXDB is used (RXBSEL is LOW), this pin should be left open.
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
XTAL1
13
I _{Crystal or external clock input. This input is not 5V tolerant.}
XTAL2
14
O _{Crystal or buffered clock output. This output may be use to drive a clock buffer which can}
drive other device(s).
PwrSave 12
I _{Power-Save (active high). This feature isolates the L202’s data bus interface from the host}
preventing other bus activities that cause higher power drain during sleep mode. See Sleep
Mode with Auto Wake-up and Power-Save Feature section for details.
ACP
20
I _{Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut}
off if the L202 is already in partial sleep mode, i.e. the crystal oscillator is stopped. See
”Section 2.15, Sleep Modes and Power-Save Feature with Wake-Up Inter-
rupt” on page 17.
I/M#
23
I _{Intel or Motorola Bus Select.}
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
RESET
35
(RESET#)
I _{When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).}
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period (see Table 16).
C2P
C2N
36
- _{Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed}
34
between these 2 pins.
C1P
C1N
39
- _{Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed}
38
between these 2 pins.
4