XR16M781 Datasheet, PDF (36/52 Pages) Exar Corporation – 1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE

XR16M781
1.62V TO 3.63V UART WITH 64-BYTE FIFO AND VLIO INTERFACE
REV. 1.0.1
4.12 Enhanced Mode Select Register (EMSR) - Write-only
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Level Count
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 12: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0] _{Scratchpad is}
0
X
X
Scratchpad
1
X
0
RX FIFO Level Counter Mode
1
0
1
TX FIFO Level Counter Mode
1
1
1
Alternate RX/TX FIFO Counter Mode
During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been
asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO
Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and
so on and so forth.
EMSR[2]: Send TX Immediately
• Logic 0 = Do not send TX immediately (default).
• Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be written to the
TX shift register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only
1 byte will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If
more than 1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.
EMSR[3]: Invert RTS in RS485 mode
• Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default).
• Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.
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