XRK39653 Datasheet, PDF (3/7 Pages) Exar Corporation – 3.3V, 8-OUTPUT ZERO DELAY BUFFER

xr
REV. P1.0.0
PIN DESCRIPTIONS
PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
NUMBER
1
2
3, 4, 5, 6
7
8
9
10
11,15, 19,
23, 27,
12, 14, 16,
18, 20, 22,
24, 26
13, 17, 21,
25, 29
28
30
31
32
NAME
AVDD
FB_IN
NC
AGND
PECL
PECL
OE
VDD
Q[7:0]
GND
QFB
PLL_EN
BYPASS
VCO_SEL
TYPE
Power
Input
pull-up
DESCRIPTION
Power supply for PLL
External PLL feedback clock input
Power
PLL ground
Input
LVPECL - pos differential reference clock
Input
LVPECL - neg differential reference clock
Input pull-down Output enable/disable and device reset
Power
Power supply
Output
Clock outputs
Power
Ground
Output
Input
Input
Input
pull-up
pull-up
pull-up
Feedback output for PLL
PLL enable/disable select
PLL and output divider bypass select
VCO divider select
Pin Name
VCO_SEL
PLL_EN
BYPASS
OE
TABLE 1: CONTROL INPUT FUNCTION TABLE
0
1
System Divide = 4 of VCO output
System Divide = 8 of VCO output
PLL is bypassed and disabled. The PECL
clock reference source drives the outputs
through the divider blocks
PLL enabled. Normal operation. VCO out-
put drives the outputs through the divider
blocks
Complete bypass of the PLL and divider
blocks. PECL reference clocks the outputs.
Normal operation. Dividers selected.
Outputs enabled
Outputs tri-stated and device reset. VCO
running at minimum frequency
Default
1
1
1
0
3