XRK32309 Datasheet, PDF (3/13 Pages) Exar Corporation – LOW-COST 3.3V ZERO DELAY BUFFER

REV. P1.0.1
PRELIMINARY
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
S2
S1
0
0
0
1
1
0
1
1
TABLE 2: SELECT INPUT DECODING
QA0-QA3
QB0-QB3
Tri-Stated
Driven
Driven
Driven
Tri-Stated
Tri-Stated
Driven
Driven
FB^[4]
Driven
Driven
Driven
Driven
OUTPUT SOURCE
PLL
PLL
Reference
PLL
NOTES:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output has an internal feedback for the PLL. The load on this output can be adjusted to change the skew
between the reference and output.
FIGURE 3. REF. INPUT TO QAX/QBX DELAY VS. LOADING DIFFERENCE BETWEEN FB AND QAX/QBX PINS
1500
1000
500
0
-30
-25
-20
-15
-10
-5
0
-500
5
10
15
20
25
30
-1000
-1500
Output Load Difference: FB Load - QAx/QBx Load (pF)
Note: Target only, actual characterization curve may be slightly different.
ZERO DELAY AND SKEW CONTROL
In order to achieve Zero Delay between the input reference and the output, all outputs, including FB, must be
equally loaded even when the FB output is not being used.
Being internally connected as the PLL feedback, the FB output's capacitive loading relative to the other
outputs can adjust the input to output delay according to the characteristic shown in Figure 3. This figure
provides a tool for mapping the required delay to the capacitive load difference required between the FB and
the Clock output of interest.
For zero output to output skew, the outputs have to be loaded equally as well.
3