XRD8785 Datasheet, PDF (3/15 Pages) Exar Corporation – CMOS 8-Bit High Speed Analog-to-Digital Converter

XRD8785
ELECTRICAL CHARACTERISTICS TABLE
UNLESS OTHERWISE SPECIFIED: AV_DD = DV_DD = 5V, FS = 15MHZ (50% DUTY CYCLE),
V_RT = 2.6V, V_RB = 0.6V, T_A = 25°C
25°C
Parameter
Symbol
Min
Typ
Max
Units Test Conditions/Comments
KEY FEATURES
Resolution
8
Bits
Sampling Rate
FS
0.1
15
20
MHz
ACCURACY
Differential Non-Linearity
DNL
+/-0.75 LSB
@ 15MHz
Differential Non-Linearity
DNL
+/-0.5
LSB
@ 10MHz
Integral Non-Linearity
INL
+/-1.5 LSB
Best Fit Line
(Max INL – Min INL)/2
Zero Scale Error
EZS
+3
LSB
Full Scale Error
EFS
-2
LSB
REFERENCE VOLTAGES
Positive Ref. Voltage
Negative Ref. Voltage
Differential Ref. Voltage³
Ladder Resistance
Ladder Temp. Coefficient
Self Bias 1
V_RT
V_RB
V _REF
R_L
R_TCO
AGND
1.0
245
2.6
0.6
350
2000
AV_DD
AV_DD
550
V
V
V
Ω
ppm/°C
V_REF = V_RT – V_RB
Short V_RB and V_RBS
Short V_RT and V_RTS
Self Bias 2
V_RB
V_RT-V_RB
0.6
V
2
V
V_RB = AGND,
V_RT
Short V_RT and V_RTS
ANALOG INPUT
2.3
V
Input Bandwidth (–1 dB)^{2, 4}
BW
50
MHz
Input Voltage Range
Input Capacitance ⁵
Aperture Delay²
DIGITAL INPUTS
V_IN
V_RB
V_RT
V
C_IN
16
pF
t_AP
3
ns
Logical “1” Voltage
Logical “0” Voltage
DC Leakage Currents ⁶
CLK
OE
V_IH
4.0
V_IL
I_IN
5
5
V
1.0
V
V_IN =DGND to DV_DD
µA
µA
Input Capacitance
5
pF
Clock Timing ( See Figure 1.)⁷
Clock Period
1/FS
50
66.7
ns
High Pulse Width
Low Pulse Width
DIGITAL OUTPUTS
Logical “1” Voltage
Logical “0” Voltage
3-state Leakage
Data Valid Delay ⁸
Data Enable Delay
Data 3-state Delay
t_PWH
25
33.3
ns
t_PWL
25
33.3
ns
C _OUT =15 pF
V_OH
4.5
V
I _LOAD = 4 mA
V_OL
0.4
V
I _LOAD = 4 mA
I_OZ
10
µA
V _OUT =DGND to DV_DD
t_DL
10
ns
t_DEN
5
ns
t_DHZ
5
ns
Rev. 3.00
3