XR16C2850CM-F Datasheet, PDF (3/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

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REV. 2.1.3
PIN DESCRIPTIONS
XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
NAME
44-PLCC
PIN #
DATA BUS INTERFACE
A2
29
A1
30
A0
31
D7
9
D6
8
D5
7
D4
6
D3
5
D2
4
D1
3
D0
2
IOR#
24
IOW#
20
CSA#
16
CSB#
17
INTA
33
INTB
32
TXRDYA#
1
RXRDYA#
34
TXRDYB#
12
48-TQFP
PIN #
26
27
28
3
2
1
48
47
46
45
44
19
15
10
11
30
29
43
31
6
TYPE
DESCRIPTION
I _{Address data lines [2:0]. These 3 address lines select one of the inter-}
nal registers in UART channel A/B during a data bus transaction.
I/O _{Data bus lines [7:0] (bidirectional).}
I _{Input/Output Read Strobe (active low). The falling edge instigates an}
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
I _{Input/Output Write Strobe (active low). The falling edge instigates an}
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
I _{UART channel A select (active low) to enable UART channel A in the}
device for data bus operation.
I _{UART channel B select (active low) to enable UART channel B in the}
device for data bus operation.
O _{UART channel A Interrupt output. The output state is defined by the}
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output is LOW when MCR[3] is set to a logic 1. INTA
is set to the three state mode and OP2A# is HIGH when MCR[3] is set
to a logic 0 (default). See MCR[3]. If this output is not used, leave it
unconnected.
O _{UART channel B Interrupt output. The output state is defined by the}
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output is LOW when MCR[3] is set to a logic 1. INTB
is set to the three state mode and OP2B# is HIGH when MCR[3] is set
to a logic 0 (default). See MCR[3]. If this output is not used, leave it
unconnected.
O UART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. See
Table 2. If this output is not used, leave it unconnected.
O _{UART channel A Receiver Ready (active low). This output provides the}
RX FIFO/RHR status for receive channel A. See Table 2. If this output
is not used, leave it unconnected.
O _{UART channel B Transmitter Ready (active low). The output provides}
the TX FIFO/THR status for transmit channel B. See Table 2. If this
output is not used, leave it unconnected.
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