XR20M1172 Datasheet, PDF (27/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
REV. 1.1.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4 BIT-3
BIT-2
BIT-1 BIT-0
COMMENT
0x0B IOState RD/WR Bit-7
Bit-6
Bit-5 Bit-4 Bit-3
Bit-2
Bit-1 Bit-0
0x0C IOIntEna RD/WR Bit-7
Bit-6
Bit-5 Bit-4 Bit-3
Bit-2
Bit-1 Bit-0
0x0D reserved -
0
0
0
0
0
0
0
0
0x0E IOControl RD/WR 0
0
0
0
UART GPIO or GPIO or IOLatch
SW Modem Modem
Reset IO Ch B IO Ch A
0x0F EFCR RD/WR Fast IR
0
Auto Auto
0
TX
RX
9-Bit
Mode
RS485 RS485
Invert Enable
Disable Disable ^Mode
0x00
0x01
0x02
DLL
DLM
DLD
RD/WR Bit-7
RD/WR Bit-7
RD/WR Bit-7
Baud Rate Generator Divisor
Bit-6
Bit-5 Bit-4 Bit-3
Bit-2
Bit-6
Bit-5 Bit-4 Bit-3
Bit-2
Bit-6
4X Mode 8X Mode
Frac-
tional
Divisor
Bit-3
Frac-
tional
Divisor
Bit-2
Bit-1 Bit-0
Bit-1 Bit-0
Frac-
tional
Divisor
Bit-1
Frac-
tional
Divisor
Bit-0
LCR[7]=1
LCR≠0xBF
LCR[7]=1
LCR≠0xBF
EFR[4]=1
Enhanced Registers
0x02
0x04
EFR
XON1
RD/WR
Auto
CTS
Enable
Auto RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
DLD
RD/WR Bit-7
Bit-6
Bit-5 Bit-4
Soft-
ware
Flow
Cntl
Bit-3
Bit-3
Software
Flow Cntl
Bit-2
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
Bit-0
LCR=0XBF
0x05 XON2 RD/WR Bit-7
Bit-6
Bit-5 Bit-4 Bit-3
Bit-2
Bit-1 Bit-0
0x06 XOFF1 RD/WR Bit-7
Bit-6
Bit-5 Bit-4 Bit-3
Bit-2
Bit-1 Bit-0
0x07 XOFF2 RD/WR Bit-7
Bit-6
Bit-5 Bit-4 Bit-3
Bit-2
Bit-1 Bit-0
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 17.
4.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 15.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
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