XR16L788_08 Datasheet, PDF (24/54 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART

XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
REV. 1.2.3
TABLE 10: TIMER CONTROL REGISTER
TIMERCNTL [0] Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNTL [1] Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2] Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3] Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [7:4] Reserved (defaults to zero).
TIMERCNTL Register
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd
Rsvd Rsvd
Rsvd
Clock Single/ Start/ INT
Select Re-trigger Stop Enable
3.1.2.1 TIMER [7:0] (default 0x00):
Reserved.
3.1.2.2 TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Reading the TIMERCNTL register will clear its
interrupt. Default value is zero upon power-up and reset.
16-Bit Timer/Counter Programmable Registers
TIMERMSB Register
TIMERLSB Register
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9 Bit-8
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
3.1.3 8XMODE [7:0] (default 0x00)
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects
normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by
selecting 8X.
8XMODE Register
Individual UART Channel 8X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
3.1.4 REGA [15:8](default 0x00)
Reserved.
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