SP508E Datasheet, PDF (23/29 Pages) Exar Corporation – Rugged 20Mbps, 8 Channel Multi-Protocol Transceiver with Programmable DCE/DTE and Termination Resistors

The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator are present.
Since both V⁺ and V^- are separately gener-
ated from V_CC; in a no-load condition V⁺ and
V^- will be symmetrical. Older charge pump
approaches that generate V^- from V⁺ will show
a decrease in the magnitude of V^- compared
to V⁺ due to the inherent inefficiencies in
the design.
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors
can be as low as 1µF with a 16V breakdown
voltage rating.
TERM_OFF FUNCTION
The SP508E contains a TERM_OFF pin
that disables all three receiver input ter-
mination networks regardless of mode.
This allows the device to be used in
monitor mode applications that are typi-
cally found in networking test equipment.
The TERM_OFF pininternally contains a
pull-down device with animpedance of over
500kΩ, which will default in a “ON” condition
during power-up if V.35 receivers are used.
The individual receiver enable line and
the SHUTDOWN mode from the decoder
will disable the termination regardless of
TERM_OFF.
LOOPBACK FUNCTION
The SP508E contains a LOOPBACK pin that
invokes a loopbackpath.This loopback path
is illustrated in Figure 46. LOOPBACKhas
an internal pull-up resistor that defaults to
normal mode during power up or if the pin is
left floating. During loopback, the driver out-
put and receiver input characteristics will still
adhere to its appropriate specifications.
There are internal pull-up devices on D0,
D1, and D2, which allow the device to be in
SHUTDOWN mode (“111”) upon power up.
However , if the device is powered -up with
the D_LATCH at a logic HIGH, the decoder
state of the SP508E will be undefined.
ESD TOLERANCE
The SP508Edevice incorporates ruggedized
ESD cells on all driver output and receiver
input pins. The ESD structure is improved
over our previous family for more rugged
applications and environments sensitive
to electrostatic discharges and associated
transients.
CTR1/CTR2 EUROPEAN COMPLIANCY
As with all of Exar’s previous multi-
protocol serial transceiver IC’s, the
drivers and receivers have been de-
signed to meet all the requirements to
NET1/NET2 and TBR2 in order to meet
CTR1/CTR2 compliancy.The SP508Eis
also tested in-house at Exar and adheres
to all the NET1/2 physical layer testing
and the ITU Series V specifications before
shipment. Please note that although the
SP508E , as with its predecessors, ad-
here to CTR1/CTR2 compliancy testing,
any complex or unusual configuration should
be double-checked to ensure CTR1/CTR2
compliance. Consult the factory for de-
tails.
DECODER AND D_LATCH FUNCTION
The SP508E contains a D_LATCH pin
that latches the data into the D0, D1,
and D2 decoder inputs. If tied to a
logic LOW (“0”), the latch is transpar-
ent, allowing the data at the decoder
inputs to propagate through and program
the SP508E accordingly. If tied to a logic
HIGH(“1”), the latch locks out the data and
preventsthe mode from changing until this
pin is brought to a logic LOW.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.comSP508E_100_072412
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