XRT86VL38_2 Datasheet, PDF (22/160 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 6: FRAMING SELECT REGISTER (FSR)
HEX ADDRESS: 0Xn107
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 Signaling update on
R/W
Superframe Boundaries
0
Enable Robbed-Bit Signaling Update on Superframe Boundary
on Both Transmit and Receive Direction
This bit enables or disables robbed-bit signaling update on the
superframe boundary for both the transmit and receive side of the
framer.
On the Receive Side:
If signaling update is enabled, signaling data on the receive side
(RxSIG pin and Signaling Array Register - RSAR) will be updated on
the superframe boundary, otherwise, signaling data will be updated
as soon as it is received.
On the Transmit Side:
If signaling update is enabled, any signaling data changes on the
transmit side will be transmitted on the superframe boundary, other-
wise, signaling data will be transmitted as soon as it is changed.
0 - Disables the signaling update feature for both transmit and
receive.
1 - Enables the signaling update feature for both transmit and
receive.
6 Force CRC Errors
R/W
0
Force CRC Errors (To the Line Side)
This bit permits the user to force the Transmit T1 Framer block to
transmit CRC errors within the outbound T1 data-stream, as depicted
below.
0 - Disables CRC error transmission on the outbound T1 stream.
1 - Enables CRC error transmission on the outbound T1 stream.
5 J1_MODE
R/W
0
J1 Mode
This bit is used to configure the device in J1 mode. Once the device
is configured in J1 mode, the following two changes will happen:
1. CRC calculation is done in J1 format. The J1 CRC6 calcula-
tion is based on the actual values of all 4632 bits in a T1 multi-
frame including Fe bits instead of assuming all Fe bits to be a
one in T1 format.
2. Receive and Transmit Yellow Alarm signal format is inter-
preted per the J1 standard. (J1-SF or J1-ESF)
0 - Configures the device in T1 mode. (Default)
1 - Configures the device in J1 mode.
NOTE: Users can select between J1-SF or J1-ESF by setting this bit
and the T1 Framing Mode Select Bits[2:0] (Bits 2-0 within
this register).
4 ONEONLY
R/W
0
Allow Only One Sync Candidate
This bit is used to specify one of the synchronization criteria that the
Receive T1 Framer block employs.
0 - Allows the Receive T1 Framer to select any one of the winners in
the matching process when there are two or more valid synchroniza-
tion patterns appear in the required time frame.
1 - Allows the Receive T1 Framer to declare success of match when
there is only one candidate left in the required time frame.
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