DAN-133 Datasheet, PDF (2/8 Pages) Exar Corporation – EXAR’S QUARTS COMPARED

DATA COMMUNICATIONS APPLICATION NOTE
DAN133
1.3 BUS TIMING DIFFERENCES
• The TL16C554A requires that the -CS pin is asserted first before the -IOR or -IOW pin and the -IOR or -IOW
pin must be de-asserted before the -CS pin is de-asserted. During a read, the Exar UART can have either
the -CS or the -IOR signal asserted first and have either signal be de-asserted first. The signals are wire-
ORed in the Exar UART, therefore the second signal asserted will initiate the read cycle and the first signal
de-asserted terminates the read cycle. The same is true during a write for -CS and -IOW. The flexibility of
the Exar QUART timing can be important in DSP, ARM, and MIPS designs.
1.4 FIRMWARE DIFFERENCES
1.4.1 Firmware Differences Between the ST16C554 and TL16C554A
The internal registers in the ST16C554 and TL16C554A are similar but with one exception:
TABLE 1: ST16C554 AND TL16C554A REGISTER SET DIFFERENCES
A2:A0 R/W
LCR Bit-7 = 0
100
R/W
ST16C554
Modem Control Register (MCR)
• Bit-5 = Not Used
TL16C554A
Modem Control Register (MCR)
• Bit-5 = Auto RTS/CTS Flow Control Enable
R = Read-Only, W = Write-Only, R/W = Read/Write
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