XRT83L38_07 Datasheet, PDF (18/87 Pages) Exar Corporation – OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
SIGNAL
NAME
CLKSEL0
CLKSEL1
CLKSEL2
LEAD # TYPE
DESCRIPTION
A8
I Clock Select inputs for Master Clock Synthesizer - Hardware mode
B8
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be
C8
used to generate a master clock from an external accurate clock source according to
the table below.
In Hardware mode, the MCLKRATE control signal is generated from the state of
EQC[4:0] inputs.
In Host mode, the state of these pins are ignored and the master frequency PLL is con-
trolled by the corresponding interface bits. See Table 36 register address 10000001
MCLKE1 MCLKT1
kHz
kHz
CLKOUT/
CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE
kHz
2048
2048
0
0
0
0
2048
2048
2048
0
0
0
1
1544
2048
1544
0
0
0
0
2048
1544
1544
0
0
1
1
1544
1544
1544
0
0
1
0
2048
2048
1544
0
0
1
1
1544
8
X
0
1
0
0
2048
8
X
0
1
0
1
1544
16
X
0
1
1
0
2048
16
X
0
1
1
1
1544
56
X
1
0
0
0
2048
56
X
1
0
0
1
1544
64
X
1
0
1
0
2048
64
X
1
0
1
1
1544
128
X
1
1
0
0
2048
128
X
1
1
0
1
1544
256
X
1
1
1
0
2048
256
X
1
1
1
1
1544
NOTE: These pins are internally pulled “Low” with a 50kΩ resistor.
15