ST16C2550 Datasheet, PDF (17/34 Pages) Exar Corporation – DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFOS

ST16C2550
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condi-
tion)
Logic 1 = Set DMA mode “1.”
Transmit operation in mode “0”:
When the 2550 is in the ST16C450 mode (FIFO’s
disabled, FCR bit-0 = logic 0) or in the FIFO mode
(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, the -TXRDY pin in
44/48 pin packages will be a logic 0. Once active the
-TXRDY pin will go to a logic 1 after the first character
is loaded into the transmit holding register.
Receive operation in mode “0”:
When the 2550 is in mode “0” (FCR bit-0 = logic 0) or
in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 =
logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin on 44/48 pin packages will go
to a logic 1 when there are no more characters in the
receiver.
Transmit operation in mode “1”:
When the 2550 is in FIFO mode ( FCR bit-0 = logic 1,
FCR bit-3 = logic 1 ), the -TXRDY pin on 44/48 pin
packages will be a logic 1 when the transmit FIFO is
completely full. It will be a logic 0 if one or more FIFO
locations are empty.
Receive operation in mode “1”:
When the 2550 is in FIFO mode (FCR bit-0 = logic 1,
FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin on 44/48 pin packages will go to a logic 0.
Once activated, it will go to a logic 1 after there are no
more characters in the FIFO.
FCR BIT 4-5:
Not Used - initialized to a logic 0.
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level = 1)
These bits are used to set the trigger level for the
receive FIFO interrupt.
An interrupt is generated when the number of charac-
ters in the FIFO equals the programmed trigger level.
However the FIFO will continue to be loaded until it is
full.
BIT-7
0
0
1
1
BIT-6
0
1
0
1
RX FIFO trigger level
01
04
08
14
Interrupt Status Register (ISR)
The 2550 provides four levels of prioritized interrupts
to minimize external software interaction. The Inter-
rupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the
ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are
acknowledged until the pending interrupt is serviced.
Whenever the interrupt status register is read, the
interrupt status is cleared. However it should be noted
that only the current pending interrupt is cleared by the
read. A lower level interrupt may be seen after reread-
ing the interrupt status bits. The Interrupt Source
Table 6 (below) shows the data values (bits 0-3) for the
four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels:
Rev. 3.20
17