SP3223ECY-L Datasheet, PDF (16/20 Pages) Exar Corporation – Intelligent 3.0V to 5.5V RS-232 Transceivers

Figure 25. ESD Test Circuit for IEC61000-4-2
The circuit model in Figures 24 and 25 rep-
resent the typical ESD testing circuit used for
all three methods. The C_S is initially charged
with the DC power supply when the first
switch (SW1) is on. Now that the capacitor
is charged, the second switch (SW2) is on
while SW1 switches off. The voltage stored
in the capacitor is then applied through R_S,
the current limiting resistor, onto the device
under test (DUT). In ESD tests, the SW2
switch is pulsed so that the device under
test receives a duration of voltage.
For the Human Body Model, the current
limiting resistor (R_S) and the source capacitor
(C_S) are 1.5kΩ an 100pF, respectively. For
IEC-61000-4-2, the current limiting resistor
(R_S) and the source capacitor (C_S) are 330Ω
an 150pF, respectively.
The higher C_S value and lower R_S value in
the IEC61000-4-2 model are more stringent
than the Human Body Model. The larger
storage capacitor injects a higher voltage
to the test point when SW2 is switched on.
The lower current limiting resistor increases
the current charge onto the test point.
30A
15A
0A
t=0ns
t=30ns
t→
Figure 26. ESD Test Waveform for IEC61000-4-2
Device PIN
TESTED
Driver Outputs
Receiver Inputs
Human Body
IEC61000-4-2
MODEL
Air Discharge Direct Contact
±15kV
±15kV
±15kV
±15kV
±8kV
±8kV
Level
4
4
Table 6. Transceiver ESD Tolerance Levels
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • www.exar.com
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SP3223E/EB/EU_101_062712