XR77103-A1R0 Datasheet, PDF (15/19 Pages) Exar Corporation – Universal PMIC 3-Output Buck Regulator

XR77103-A1R0
Applications Information (Continued)
Out-of-Phase Operation
Channels 1 and 2 operate in phase while channel 3 operates
180 degrees out-of-phase with the other two converters
(see Figure 30). This enables the system, having less
input ripple, to lower component cost, save board space
and reduce EMI.
LX1
LX2
LX3
Figure 30. Out-of-Phase Operation
Two Buck Regulators in Parallel Operation
(Current Sharing)
The XR77103-A1R0 can be used in parallel operation
to increase output current capacity. To enable this,
a user needs:
■■ To connect V_OUT2 and V_OUT3 together.
■■ To connect COMP2 and COMP3 together.
■■ Regulate the channels 2 and 3 to the same V_OUT.
Then, the channels 2 and 3 will run in parallel and load
current is shared in average.
BUCK2
LX2
LX2
VFB2
COMP2
VOUT
BUCK3
COMP3
LX3
LX3
VFB3
Figure 31. Parallel Operation
Power Good
The PGOOD pin is an open drain output. The PGOOD
pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled
up when all three buck converters’ outputs are more than
90% of their nominal output voltage and the PGOOD reset
timer expires. The polarity of the PGOOD is active high.
The PGOOD reset time is 1s.
Thermal Design
Proper thermal design is critical in controlling device
temperatures and in achieving robust designs. There are
a number of factors that affect the thermal performance.
One key factor is the temperature rise of the devices in
the package, which is a function of the thermal resistances
of the devices inside the package and the power
being dissipated.
The thermal resistance of the XR77103-A1R0 (30°C/W)
is specified in the Operating Conditions section of
this datasheet. The θ_JA thermal resistance specification is
based on the XR77103-A1R0 evaluation board operating
without forced airflow. Since the actual board design in the
final application will be different, the thermal resistances in
the final design may be different from those specified.
The package thermal derating and power loss curves are
shown in Figures 20 through 26. These correspond to input
voltages of 12V and 5V.
Layout Guidelines
Proper PCB layout is crucial in order to obtain a good
thermal and electrical performance.
For thermal considerations it is essential to use a number
of thermal vias to connect the central thermal pad to the
ground layer(s).
In order to achieve good electrical and noise performance
following steps are recommended:
■■ Place the output inductor close to the LX pins and
minimize the area of the connection. Doing this
on the top layer is advisable.
■■ Central thermal pad shall be connected to the
power ground connections to as many layers
as possible.
■■ Output filtering capacitor shall share the
same power ground connection as the input
filtering capacitor. Connection to the signal
ground plane shall be done with vias placed at
the output filtering capacitors.
■■ AC current loops formed by input filtering
capacitors, output filtering capacitors, output
inductors, and the regulator pins shall
be minimized.
■■ GND, AGND, DGND pins shall be connected to
the signal ground plane.
■■ Compensation networks shall be placed close to
the pins and referenced to the signal ground.
■■ V_CC bypass capacitor shall be placed close to
the pin.
REV1A
15/19