ST16C452CJ68PS-F Datasheet, PDF (15/30 Pages) Exar Corporation – DUAL UART WITH PARALLEL PRINTER PORT

ST16C452/452PS
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the INT A,B output pins.
IER BIT-0:
This interrupt will be issued when the RHR is full or is
cleared when the RHR is empty.
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
This interrupt will be issued whenever the THR is
empty and is associated with bit-1 in the LSR register.
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
This interrupt will be issued whenever a fully as-
sembled receive character is transferred from the
RSR to the RHR, i.e., data ready, LSR bit-0.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7:
Not Used - initialized to a logic 0.
Interrupt Status Register (ISR)
The 452/452PS provides four levels of prioritized
interrupts to minimize external software interaction.
The Interrupt Status Register (ISR) provides the user
with four interrupt status bits. Performing a read cycle
on the ISR will provide the user with the highest
pending interrupt level to be serviced. No other inter-
rupts are acknowledged until the pending interrupt is
serviced. Whenever the interrupt status register is
read, the interrupt status is cleared. However it should
be noted that only the current pending interrupt is
cleared by the read. A lower level interrupt may be
seen after rereading the interrupt status bits. The
Interrupt Source Table 8 (below) shows the data
values (bits 0-3) for the four prioritized interrupt levels
and the interrupt sources associated with each of
these interrupt levels:
Table 8, INTERRUPT SOURCE TABLE
Priority
[ISR BITS]
Level Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt
1
0 1 1 0 LSR (Receiver Line Status Register)
2
0 1 0 0 RXRDY (Received Data Ready)
3
0 0 1 0 TXRDY (Transmitter Holding Register Empty)
4
0 0 0 0 MSR (Modem Status Register)
Rev. 3.20
15