XRT86SH328_07 Datasheet, PDF (149/339 Pages) Exar Corporation – 28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET

PRELIMINARY
XRT86SH328
REV. P1.0.6 28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
NOTE: For normal operation, the user should set this register to 0x00.
TABLE 178: TRANSMIT STS-1/STS-3 TRANSPORT - TRANSMIT B2 BYTE ERROR MASK REGISTER (ADDRESS
LOCATION = 0X0727)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Transmit B2 Error
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT [7:1] - Unused]
BIT 0 - Transmit B2 Byte Error Enable
This READ/WRITE bit-field is used to configure the Transmit STS-1/STS-3 TOH Processor block to perform the XOR
operation with the contents of the Transmit STS-1/STS-3 Transport -Transmit B2 Bit Error Mask Register (Address
Location = 0x072B)
` 0 - Disables the XOR operation. In this case, the Transmit STS-1/STS-3 TOH Processor block will NOT perform the
XOR operation with the Transmit STS-1/STS-3 Transport - Transmit B2 Bit Error Mask Register. As a consequence,
the Transmit STS-1/STS-3 TOH Processor block will transmit a continuous stream of STS-1s with no B2 byte errors.
` 1 - Enables the XOR operation. In this setting, the Transmit STS-1/STS-3 TOH Processor will perform the XOR
operation of the value of the B2 byte (within the outbound STS-1 or STS-3 frame) with the contents within the Transmit
STS-1/STS-3 Transport - Transmit B2 Bit Error Mask register.
TABLE 179: TRANSMIT STS-1/STS-3 TRANSPORT - TRANSMIT B2 BIT ERROR MASK REGISTER (ADDRESS
LOCATION= 0X072B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_B2_Error_Mask[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT [7:0] - Transmit B2 Error Mask-Byte
These READ/WRITE bit-fields are used to insert B2 byte errors into the outbound STS-1 or STS-3 Data-stream, for
diagnostic purposes.
If BIT 0 (Transmit B2 Error Enable) within the Transmit STS-1/STS-3 Transport - Transmit B2 Byte Error Register
(Address Location = 0xN927) is set to 1, then Transmit STS-1/STS-3 TOH Processor block will be configured to perform
an XOR operation between the contents of this register, with the contents of the outbound B2 byte. The results of this
calculation is written back into the B2 byte position, within the outbound STS-1 or STS-3 Data. Hence, for every bit
(within this register) that is set to 1, the corresponding bit (within the outbound B2 byte) will be erred.
NOTES:
1. 1. For normal (e.g., un-erred) operation, the user should ensure that this register is set to the value 0x00.
2. These register bits are ignored unless BIT 0 (Transmit B2 Error Enable), within the Transmit STS-1/STS-
3 Transport - Transmit B2 Byte Error Register has been set to 1.
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