XRT86SH221 Datasheet, PDF (142/353 Pages) Exar Corporation – SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU

XRT86SH221
PRELIMINARY
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
• When the Receive STM-0 TOH Processor block declares the LOF defect condition
• When the Receive STM-0 TOH Processor block clears the LOF defect condition.
0 - Disables the Change of LOF Defect Condition Interrupt.
1 - Enables the Change of LOF Defect Condition Interrupt.
BIT 1 - Change of SEF Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change of SEF Defect Condition Interrupt. If this
interrupt is enabled, then the XRT86SH328 will generate an interrupt in response to either of the following conditions.
• When the Receive STM-0 TOH Processor block declares the SEF defect condition.
• When the Receive STM-0 TOH Processor block clears the SEF defect condition.
0 - Disables the Change of SEF Defect Condition Interrupt.
1 - Enables the Change of SEF Defect Condition Interrupt.
BIT 0 - Change of Loss of Signal (LOS) Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change of LOF Defect Condition interrupt. If this
interrupt is enabled, then the XRT86SH328 will generate an interrupt in response to either of the following conditions.
• When the Receive STM-0 TOH Processor block declares the LOF defect condition.
• When the Receive STM-0 TOH Processor block clears the LOF defect condition.
0 - Disables the Change of LOF Defect Condition Interrupt.
1 - Enables the Change of LOF Defect Condition Interrupt.
TABLE 60: RECEIVE STM-0/STM-1 TRANSPORT - B1 BYTE ERROR COUNT REGISTER 3 (B1BECR3 = 0X0210)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Byte_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT [7:0] - B1 Byte Error Count - MSB
This RESET-upon-READ register, along with Receive STM-0 Transport - B1 Byte Error Count Register - Bytes 2
through 0, function as a 32 bit counter, which is incremented anytime the Receive STM-0 TOH Processor block detects
a B1 byte error.
NOTES:
1. If the Receive STM-0 TOH Processor Block is configured to count B1 byte errors on a per-bit basis, then
it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming STM-0 frame)
that are in error
2. If the Receive STM-0 TOH Processor block is configured to count B1 byte errors on a per-frame basis,
then it will increment this 32 bit counter each time that it receives an STM-0 frame that contains an erred B1
byte.
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