XRT82D20 Datasheet, PDF (14/27 Pages) Exar Corporation – SINGLE CHANNEL E1 LINE INTERFACE UNIT

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SINGLE CHANNEL LINE INTERFACE UNIT XRT82D20
REV. 1.0.7
SYSTEM DESCRIPTION
The XRT82D20 is a single channel E1 transceiver
that provides an electrical interface for 2.048Mbps ap-
plications. XRT82D20 includes a receive circuit that
converts an ITU-T G.703 compliant bipolar signal into
a TTL compatible logic levels. The receiver also in-
cludes an LOS (Loss of Signal) detection circuit.
Similarly, in the Transmit Direction, the Transmitter
converts TTL compatible logic levels into a G.703
compatible bipolar signal.
The XRT82D20 consists of both a Receive Section,
Jitter Attenuator and Transmit Section; each of these
sections will be discussed below.
1.0 THE RECEIVE SECTION
At the receiver input, cable attenuated AMI signal can
be coupled to the receiver using a capacitor or trans-
former. The receive data first goes through the peak
detector and data slicer for accurate data recov-
ery.The digital representation of the AMI signals go to
the clock recovery circuit for timing recovery and sub-
sequently to the decoder (if selected) for HDB3 de-
coding before being output to the RPOS/RData and
RNEG/LCV pins. The digital data output can be in
NRZ or RZ format depending the mode of operation
selected and with the option to be in dual-rail or single
rail mode. Clock timing recovery of the line interface
is accomplished by means of a digital PLL scheme
which has high input jitter tolerance.
The purpose of the Receive Output Interface block is
to interface directly with the Receiving Terminal
Equipment. The Receive Output Interface block out-
puts the data (which has been recovered from the in-
coming line signal) to the Receive Terminal Equip-
ment via the RPOS and RNEG output pins.
If the Receive Section of the XRT82D20 has received
a Positive-Polarity pulse, via the RTIP and
RRing input pins, then the Receive Output Interface
will output a pulse at the RPOS output pin.
Similarly, if the Receive Section of the XRT82D20 has
received a Negative-Polarity pulse, via the RTIP and
RRing input pins, then the Receive Output Interface
will output a pulse at the RNEG output pin.
1.1 JITTER ATTENUATOR
To reduce frequency jitter in the transmit clock or re-
ceive clock, a crystal-less jitter attenuator is provided.
The jitter attenuator can be selected either in the
transmit or receive path or it can be disabled.
1.2 THE TRANSMIT SECTION
In general, the purpose of the Transmit Section (with-
in the XRT82D20) is to accept TTL/CMOS level digital
data (from the Terminal Equipment), and to encode it
into a format such that it can:
1. Be efficiently transmitted over coaxial- or twisted
pair cable at the E1 data rate; and
2. Be reliably received by the Remote Terminal
Equipment at the other end of the E1 data link.
3. Comply with the ITU-T G.703 pulse template
requirements, for E1 applications
A 2.048 MHz clock is applied to the TClk input pin
and NRZ data at the TPOS and TNEG input pins.
The Transmit Input Interface circuit will sample the
data, at the TPOS and TNEG input pins, upon the fall-
ing edge of TClk, as illustrated in Figure 8 below.
FIGURE 8. ILLUSTRATION ON HOW THE XRT82D20 SAMPLES THE DATA ON THE TPOS AND TNEG INPUT PINS
tSU
tHO
TPOS
TNEG
TClk
In general, if the XRT82D20 samples a “1” on the
TPOS input pin, then the Transmit Section will ulti-
mately generate a positive polarity pulse via the TTIP
and TRing output pins (across a 1:2 transformer).
Conversely, if the XRT82D20 samples a “1” on the
TNEG input pin, then the Transmit Section of the de-
vice will ultimately generate a negative polarity pulse
via the TTIP and TRing output pins (across a 1:2
transformer).
1.3 THE PULSE SHAPING CIRCUIT
The purpose of the Transmit Pulse Shaping circuit is
to generate Transmit Output pulses that comply with
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