XR77103-A0R5 Datasheet, PDF (14/19 Pages) Exar Corporation – Universal PMIC 3-Output Buck Regulator

XR77103-A0R5
Applications Information
Operation
XR77103-A0R5 is a power management IC with three
step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous
conversion with higher efficiency. XR77103-A0R5 can
support 4.5V to 14V input supply, high load current,
500kHz clocking. The buck converters have a PSM
mode which can improve power dissipation during
light loads. Alternatively, the device implements a constant
frequency mode. The SYNC pin also provides a means
to synchronize the power converter to an external signal.
Input ripple is reduced by 180 degree out-of-phase
operation among converters. All three buck converters
have peak current mode control which simplifies external
frequency compensation. Each buck converter has peak
inductor current limit of 3.5A. The device has a power good
comparator monitoring the output voltage. Soft-start for
each converter is 6ms. All outputs start up once EN pin is
set high.
Output Voltage Setting
Output voltage is set externally using an external
resistor divider. Output voltage is determined by the
following equation.
VOUTX = 0.8V x
1+
R1
R2
VOUTX
R1
XR77103-A0R5
R2
Figure 28. Output Voltage Setting
This can make the device applicable to AVS (automatic
voltage scaling) system. Output voltage can be adjusted
automatically by external DC voltage. Figure 29 shows
application circuit of supply for AVS system.
XR77103-A0R5
VFBX
VOUTX
R1
RDAC
R2
AVS SUPPLY
SOC
VDAC _{PVT MNT}
Figure 29. AVS Control
Frequency Compensation
In order to properly frequency compensate the device,
the following component selection is recommended.
V_IN
(V)
12/5.0
V_OUT
(V)
1.0
L
(μH)
2.2
C_OUT
(µF)
22 x 3
R_COMP
(kΩ)
10
C_COMP
(nF)
4.7
12/5.0
1.2
2.2
22 x 3
10
4.7
12/5.0
1.5
3.3
22 x 3
20
4.7
12/5.0
1.8
3.3
22 x 2
20
4.7
12/5.0
2.5
4.7
22 x 2
20
4.7
12/5.0
3.3
4.7
22 x 1
20
4.7
12
5.0
6.8
22 x 1
20
4.7
Synchronization
The status of the SYNC pin will be ignored during start-
up and the XR77103-A0R5’s control will only synchronize
to an external signal after the PGOOD signal is asserted.
When synchronization is applied, the sync pulse frequency
must be higher than the PWM oscillator frequency
(525kHz) to allow the external signal trumping the oscillator
pulse reliably. When synchronization is not applied, the
SYNC pin should be connected to signal ground.
Although the device can lock to external clock running up to
2.31MHz, doing this will alter the timing characteristics and
degrade thermal performance.
REV1A
14/19