XR76116 Datasheet, PDF (14/19 Pages) Exar Corporation – PowerBloxTM 15A and 20A Synchronous

XR76116/20
Applications Information (Continued)
Overcurrent Protection (OCP)
If the load current exceeds the programmed overcurrent
threshold I_OCP for four consecutive switching cycles,
the regulator enters the hiccup mode of operation.
In hiccup mode the MOSFET gates are turned off for 110ms
(hiccup timeout). Following the hiccup timeout a soft-start
is attempted. If OCP persists, hiccup timeout will repeat.
The regulator will remain in hiccup mode until load current
is reduced below the programmed I_OCP. In order to program
overcurrent protection use the following equation:
(IOCP + (0.5 × 'IL))
RLIM =
ILIM
+ 0.16kΩ
RDS
Where:
■ R_LIM is resistor value in kΩ for programming I_OCP
■ I_OCP is the overcurrent value to be programmed
■ ΔI_L is the peak-to-peak inductor current ripple
■ I_LIM/R_DS is the minimum value of the parameter
specified in the tabulated data
■ I_LIM/R_DS = 6.3uA/mΩ (XR76116)
■ I_LIM/R_DS = 14.5uA/mΩ (XR76120)
■ 0.16kΩ accounts for OCP comparator offset
The above equation is for worst-case analysis and
safeguards against premature OCP. Typical value of I_OCP,
for a given R_LIM, will be higher than that predicted by
the above equation. Graph of calculated I_OCP vs. R_LIM is
compared to typical I_OCP in Figures 27 and 28.
Short-Circuit Protection (SCP)
If the output voltage drops below 60% of its programmed
value (i.e., FB drops below 0.36V), the regulator will enter
hiccup mode. Hiccup mode will persist until short-circuit
is removed. The SCP circuit becomes active at the end
of soft-start. Hiccup mode and short-circuit recovery
waveform is shown in Figure 20.
Over Temperature Protection (OTP)
OTP triggers at a nominal controller temperature of 138°C.
The gates of the switching FET and the synchronous FET
are turned off. When controller temperature cools down to
123°C, soft-start is initiated and regular operation resumes.
Overvoltage Protection (OVP)
The output OVP function detects an overvoltage condition
on V_OUT of the regulator. OVP is achieved by comparing
the voltage at VSNS pin to an OVP threshold voltage
set at 1.2xV_REF. When VSNS voltage exceeds the OVP
threshold, an internal overvoltage signal asserts after 1us
(typical). This OVP signal latches off the high-side FET,
turns on the low-side FET and also asserts PGOOD low.
The low-side FET remains on to discharge the output
capacitor until VSNS voltage drops below 1.15 x V_REF.
Then low-side FET turns off to prevent complete discharge
of V_OUT. The high-side and low-side FETs remain latched
off until V_IN or EN is recycled. In order to use this feature,
connect VSNS to V_OUT with a resistor divider as shown in
the application circuit. Use the same resistor divider value
that was used for programming V_OUT.
Programming the Output Voltage
Use a voltage divider as shown in Figure 1 to program the
output voltage V_OUT.
R1 = R2 x
VOUT
0.6
–1
The recommended value for R2 is 2kΩ.
Programming the Soft-Start
Place a capacitor C_SS between the SS and AGND pins to
program the soft-start. In order to program a soft-start time
of t_SS, calculate the required capacitance C_SS from the
following equation:
CSS = tSS x
10μA
0.6V
Pre-Bias Startup
XR76116/20 has the capability to startup into a pre-charged
output. Typical pre-bias startup waveforms are shown in
Figure 19.
Maximum Allowable Voltage Ripple at FB Pin
The steady-state voltage ripple at feedback pin FB
(V_FB,_RIPPLE) must not exceed 50mV in order for the
Regulator to function correctly. If V_FB,_RIPPLE is larger than
50mV then C_OUT and/or L should be increased as necessary
in order to keep the V_FB,_RIPPLE below 50mV.
REV1A
14/19