XR16V2752 Datasheet, PDF (14/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16V2752
PRELIMINARY
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X Clock
(EM SR bit-7)
Receive Data Shift
Register (RSR)
D ata Bit
V a lid a tio n
REV. P1.0.0
Receive Data Characters
R eceive
Data Byte
and Errors
E rror
Tags in
LSR bits
4:2
Receive Data
H olding R egister
(R H R )
RHR Interrupt (ISR bit-2)
R X FIF O 1
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X Clock
(EMSR bit-7)
64 bytes by 11-bit
wide
F IFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive
Data FIFO
R e c e iv e
Data
Data Bit
Validation
Receive Data Characters
E xam ple
- :RX FIFO trigger level selected at 16
b yte s
Data falls to
8
(See Note Below)
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
FIFO
Trigger=16
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to
24
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RXFIFO1
NOTE: Table-B selected as Trigger Table for Figure 9 (Table 10).
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