XR76201 Datasheet, PDF (13/16 Pages) Exar Corporation – 40V PowerBloxTM 1.5A Synchronous Step-Down COT Regulator

RON =
RORL_NIM=
0=V.9O(₀7I_V^UO_.9OxTC_{7(UP3fxT.×0}^–_{f55[–×(92[m.(152Ω0.5}^×_-)10×+1) ⁰₁₈^-₀⁸_m)-8^×V_{) ×}^VI_V^N_IN^] _]
(3.0I5_LI×_M10^-10)
A_PPrlp_aocp_gerli_aac_ma_cRmat_Li_pIio_RMnaLn_cgI=Mis_tto(_h=IO_rI_en_(RCCIO1PSf_SCo_=×oPSr_fR5×tm_Ib-92L_S5m_eIIM×a_9LttΩ_mIawt_M)i_rΩeo_t+V0_)eOn_+.8_n6UmV8T(_tmhCV_eV–o_S1n_Sti_an_nu_de_Ad_G) _{ND pins to}
program the soft-start. In order to program a soft-start time
of TSS, calculate the required capacitance CSS from the
following equatio_Rn_1R:_{=1CR=S2SR×2=×tSV0SO.V60×UO.VT6UVT10–0.6–µ1VA1}
π ^{FAocenefreeatehdmde-Fi-cEfooqrorwwuuiatavpraruddletcCnacCtaapCFSppaFSeaCacS=rSiccti=Soeiittorst=}2^oS(rrR×^{CSstS(eF×SCaFs×r}×^F)ies1Fm0tR0^{).a1u1061aµ0n.sVAy6}x^µceVAbe7^dex^(fEnofL^eSr_C^cRCe)sO^osU^afT^{rCytOhdUeeTnp.eaInf doCinn}F^lgyF
is necessary. Calculate C_FF from:
CFF_CF=_F
=₂
×₂
×^π
π^×
1₁
×^R1R1^x
x⁷
7^x
x^fLf^C_LC
where:
π ^■■
R1
is
the
res^fLis^Cto⁼r
that
2x
1
is_xp_√ar_La_xlle_Cl_Ow_UTith
C_FF
■■ f_LC is calculated by the equation below:
fLCfL=_C
=
2
x²Ï€^x
π_x
11
√^{x √}L ^Lx
x_COC_UOTUT
XR76201
Maximum Allowable Voltage Ripple at FB Pin
Note that the steady-state voltage ripple at feedback pin
FB (V_FB,RIPPLE) must not exceed 50mV in order for the
regulator to function correctly. If V_FB,RIPPLE is larger than
50mV then C_OUT should be increased as necessary in order
to keep the V_FB,RIPPLE below 50mV.
Feed-Forward Resistor (R_FF)
FET switching noise may couple to V_OUT through the parasitic
capacitance across the inductor, and to the FB pin via C_FF.
Excessive noise at FB will cause poor load regulation.
To solve this problem place a resistor R_FF in series
with C_FF. R_FF value up to 2% of R1 is acceptable.
f_LC frequency must be less than 11kHz when using ceramic
C_OUT. If necessary, increase L and/or C_OUT in order to meet
this constraint
When using capacitors with higher ESR, such as
PANASONIC TPE series, a C_FF is not required provided
following conditions are met:
1.The frequency of output filter LC double-pole f_LC
should be less than 11kHz
2.The frequency of ESR Zero f_ZERO,ESR should be
at least five times larger than f_LC
Note that if f_ZERO,ESR is less than 5 x f_LC, then it is
recommended to set the f_LC at less than 2kHz. C_FF is still
not required.
REV1A
13/16