XRT86VL32_1 Datasheet, PDF (12/65 Pages) Exar Corporation – DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
REV. V1.2.0
SIGNAL NAME
TxSYNC0/
TxNEG0
TxSYNC2/
TxNEG2
BALL#
D9
L15
TYPE
I/O
OUTPUT
DRIVE(MA)
DESCRIPTION
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Transmit Single Frame Sync Pulse (TxSYNCn) / Transmit
Negative Digital Input (TxNEGn):
The exact function of these pins depends on the mode of opera-
tion selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxSYNCn:
These TxSYNCn pins are used to indicate the single frame
boundary within an outbound T1/E1 frame. In both DS1 or E1
mode, the single frame boundary repeats every 125 microsec-
onds (8kHz).
In DS1/E1 base rate, TxSYNCn can be configured as either input
or output as described below.
When TxSYNCn is configured as an Input:
Users must provide a signal which must pulse "High" for one
period of TxSERCLK during the first bit of an outbound DS1/E1
frame. It is imperative that the TxSYNC input signal be synchro-
nized with the TxSERCLK input signal.
When TxSYNCn is configured as an Output:
The transmit T1/E1 framer will output a signal which pulses "High"
for one period of TxSERCLK during the first bit of an outbound
DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - TxSYNCn as INPUT
ONLY:
In this mode, TxSYNCn must be an input regardless of the clock
source that is chosen to be the timing source for the transmit
framer. In 2.048MVIP/4.096/8.192MHz high-speed modes,
TxSYNCn pins must be pulsed ’High’ for one period of TxSERCLK
during the first bit of the outbound T1/E1 frame. In HMVIP mode,
TxSYNC0 must be pulsed ’High’ for 4 clock cycles of the TxM-
SYNC/TxINCLK signal in the position of the first two and the last
two bits of a multiplexed frame. In H.100 mode, TxSYNC0 must
be pulsed ’High’ for 2 clock cycles of the TxMSYNC/TxINCLK sig-
nal in the position of the first and the last bit of a multiplexed
frame.
DS1 or E1 Framer Bypass Mode - TxNEGn
In this mode, TxSYNCn is used as the negative digital input pin
(TxNEG) to the LIU.
NOTE:
*High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP,
H.100, Bit-multiplexed modes, and (For T1 only)
12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped into
an E1 frame by ignoring every fourth time slot (don’t
care).
NOTE: These 8 pins are internally pulled “Low” for each channel.
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