XRT86VL30 Datasheet, PDF (110/188 Pages) Exar Corporation – SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

XRT86VL30
SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. 1.0.0
TABLE 99: PMON TRANSMIT SLIP COUNTER (TSC)
HEX ADDRESS: 0X090F
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 TxSLIP[7]
6 TxSLIP[6]
5 TxSLIP[5]
4 TxSLIP[4]
3 TxSLIP[3]
RUR
RUR
RUR
RUR
RUR
0
Performance Monitor - Transmit Slip Counter (8-bit Counter)
0
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Transmit Slip events have been detected by the E1
0
Framer since the last read of this register.
NOTE: A slip event is defined as a replication or deletion of a E1
0
frame by the transmit slip buffer.
0
2 TxSLIP[2]
RUR
0
1 TxSLIP[1]
RUR
0
0 TxSLIP[0]
RUR
0
TABLE 100: PMON EXCESSIVE ZERO VIOLATION COUNTER MSB (EZVCU)
HEX ADDRESS: 0X0910
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 EZVC[15]
6 EZVC[14]
5 EZVC[13]
4 EZVC[12]
3 EZVC[11]
2 EZVC[10]
1 EZVC[9]
0 EZVC[8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
Performance Monitor - E1 Excessive Zero Violation 16-Bit
Counter - Upper Byte:
0
These RESET-upon-READ bits, along with that within the “PMON
0
E1 Excessive Zero Violation Counter Register LSB” combine to
reflect the cumulative number of instances that the ReceiveE1
0
Excessive Zero Violation has been detected by the Receive E1
Framer block since the last read of this register.
0
This register contains the Most Significant byte of this 16-bit of the
0
Receive E1 Excessive Zero Violation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
0
counter first before reading the LSB counter in order to read
0
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
TABLE 101: PMON EXCESSIVE ZERO VIOLATION COUNTER LSB (EZVCL)
HEX ADDRESS: 0X0911
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 EZVC[7]
6 EZVC[6]
5 EZVC[5]
4 EZVC[4]
3 EZVC[3]
2 EZVC[2]
1 EZVC[1]
0 EZVC[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
Performance Monitor - E1 Excessive Zero Violation 16-Bit
Counter - Lower Byte:
0
These RESET-upon-READ bits, along with that within the “PMON
0
E1 Excessive Zero Violation Counter Register MSB” combine to
reflect the cumulative number of instances that the ReceiveE1
0
Excessive Zero Violation has been detected by the Receive E1
Framer block since the last read of this register.
0
This register contains the Least Significant byte of this 16-bit of the
0
Receive E1 Excessive Zero Violation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
0
counter first before reading the LSB counter in order to read
0
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
105