XRT86VL3X Datasheet, PDF (11/149 Pages) Exar Corporation – T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

XRT86VL3X
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
1.0 GENERAL DESCRIPTION AND INTERFACE
The XRT86VL3x supports multiple interfaces for various modes of operation. The purpose of this section is to
present a general overview of the common interfaces and their connection diagrams. Each mode will be
described in full detail in later sections of the datasheet.
NOTE: For a brief tutorial on Framing Formats, see Appendix A in the back of this document.
1.1 Physical Interface
The Line Interface Unit generates/receives standard return-to-zero (RZ) signals to the line interface for T1/E1/
J1 twisted pair or E1 coaxial cable. The physical interface is optimized by placing the terminating impedance
inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external
components necessary in system design. The transmitter outputs only require one DC blocking capacitor of
0.68µF and a 1:2 step-up transformer. The receive path inputs only require one bypass capacitor of 0.1µF
connected to the center tap (CT) of the transformer and a 1:1 transformer. The receive CT bypass capacitor is
required for Long Haul Applications, and recommended for Short Haul Applications. Figure 2 shows the
typical connection diagram for the LIU transmitters. Figure 3 shows a typical connection diagram for the LIU
receivers.
FIGURE 2. LIU TRANSMIT CONNECTION DIAGRAM USING INTERNAL TERMINATION
XRT86VL3x LIU
T_TIP
Transmitter
Output
T_RING
Internal Impedance
1:2
C=0.68uF
Line Interface T1/E1/J1
One Bill of Materials
FIGURE 3. LIU RECEIVE CONNECTION DIAGRAM USING INTERNAL TERMINATION
XRT86VL3x LIU
R_TIP
Receiver
Input
R _RING
Internal Impedance
0.1µF
1:1
Line Interface T1/E1/J1
One Bill of Materials
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