SP3220EUEY-L-TR Datasheet, PDF (11/20 Pages) Exar Corporation – 3.0V to +5.5V RS-232 Driver/Receiver Pair

Charge Pump
The charge pump is an Exar-patended
design (U.S. 5,306,954) and uses a unique
approach compared to older less-efficient
designs. The charge pump still requires four
external capacitors, but uses a four-phase
voltage shifting technique to attain sym-
metrical 5.5V power supplies. The internal
power supply consists of a regulated dual
charge pump that provides output voltages
of +/-5.5V regardless of the input voltage
(Vcc) over the +3.0V to +5.5V range.
In most circumstances, decoupling the
power supply can be achieved adequately
using a 0.1µF bypass capacitor at C5 (refer
to figures 6 and 7). In applications that are
sensitive to power-supply noise, decouple
Vcc to ground with a capacitor of the same
value as charge-pump capacitor C1. Physi-
cally connect bypass capacitor as close to
the IC as possible.
The charge pump operates in a discontinu-
ous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
output voltages exceed a magnitude of 5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shift-
ing. A description of each phase follows.
Phase 1
— V_SS charge storage — During this phase
of the clock cycle, the positive side of capaci-
tors C₁ and C₂ are initially charged to V_CC.
Cin_l⁺_Cis1–tihsetrnasnwsfietcrhreedd
to
to
GND and the charge
C_2–. Since C₂⁺ is con-
nected to V_CC, the voltage potential across
capacitor C₂ is now 2 times V_CC.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of
C₂ to GND. This transfers a negative gener-
ated voltage to C₃. This generated voltage is
regulated to a minimum voltage of -5.5V.
DESCRIPTION
Simultaneous with the transfer of the volt-
age to C₃, the positive side of capacitor C₁
is switched to V_CC and the negative side is
connected to GND.
Phase 3
— V_DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C₁ produces –V_CC in
the negative terminal of C₁, which is applied
to the negative side of capacitor C₂. Since
C₂⁺ is at V_CC, the voltage potential across C₂
is 2 times V_CC.
Phase 4
— V_DD transfer — The fourth phase of
the clock connects the negative terminal
of C₂ to GND, and transfers this positive
generated voltage across C₂ to C₄, the
V_DD storage capacitor. This voltage is
regulated to +5.5V. At this voltage, the in-
ternal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the
positive side of capacitor C₁ is switched
to V_CC and the negative side is con-
nected to GND, allowing the charge
pump cycle to begin again. The charge
pump cycle will continue as long as the
operational conditions for the internal
oscillator are present.
Since both V⁺ and V^– are separately gener-
ated from V_CC, in a no–load condition V⁺
and V^– will be symmetrical. Older charge
pump approaches that generate V^– from
V⁺ will show a decrease in the magnitude
of V^– compared to V⁺ due to the inherent
inefficiencies in the design.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
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SP3220E_EB_EU_102_102016