XR32220_17 Datasheet, PDF (10/15 Pages) Exar Corporation – 2-Driver/2-Receiver Intelligent RS-232 Transceiver with 1.65V to 5.5V Interface

XR32220
Applications Information (Continued)
Phase 2
V- transfer — Phase two of the clock connects the negative
terminal of C2 to the VSS storage capacitor and the positive
terminal of C2 to GND. This transfers a negative generated
voltage to C3. This generated voltage is regulated to a
minimum voltage of -5.5V. Simultaneous with the transfer
of the voltage to C3, the positive side of capacitor C1 is
switched to V_CC and the negative side is connected to GND.
VCC
C1
C2
-5.5V
C4
V+ Storage Capacitor
V- Storage Capacitor
C3
Figure 11. Charge Pump - Phase 2
Phase 4
V+ transfer — The fourth phase of the clock connects
the negative terminal of C2 to GND, and transfers this
positive generated voltage across C2 to C4, the V+ storage
capacitor. This voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous with the
transfer of the voltage to C4, the positive side of capacitor
C1 is switched to V_CC and the negative side is connected
to GND, allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as the
operational conditions for the internal oscillator are present.
VCC
+5.5V
C1
C2
C4
V+ Storage Capacitor
V- Storage Capacitor
C3
Phase 3
V+ charge storage — The third phase of the clock is identical
to the first phase — the charge transferred in C1 produces
–V_CC in the negative terminal of C1, which is applied to
the negative side of capacitor C2. Since C2+ is at V_CC,
the voltage potential across C2 is 2 times V_CC.
VCC
C1
-VCC
+VCC
C2
-VCC
C4
V+ Storage Capacitor
V- Storage Capacitor
C3
Figure 12. Charge Pump - Phase 3
Figure 13. Charge Pump - Phase 4
Since both V+ and V– are separately generated from V_CC,
in a no–load condition V+ and V– will be symmetrical.
Older charge pump approaches that generate V– from V+
will show a decrease in the magnitude of V– compared to
V+ due to the inherent inefficiencies in the design. The clock
rate for the charge pump typically operates at greater than
250kHz. The external capacitors can be as low as 0.1μF
with a 16V breakdown voltage rating.
The Exar-patented charge pumps are designed to operate
reliably with a range of low cost capacitors. Either polarized
or non polarized capacitors may be used. If polarized
capacitors are used they should be oriented as shown in
the Typical Applications Circuit. The V+ capacitor may be
connected to either ground or V_CC (polarity reversed.)
The charge pump operates with 0.1μF capacitors for
3.3V operation. For other supply voltages, see the table
for required capacitor values. Do not use values smaller
than those listed. Increasing the capacitor values (e.g., by
doubling in value) reduces ripple on the transmitter outputs
and may slightly reduce power consumption. C2, C3, and
C4 can be increased without changing C1’s value.
REV1B
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