SP3221E Datasheet, PDF (10/20 Pages) Sipex Corporation – Intelligent +3.0V to +5.5V RS-232 Transceiver

Charge Pump
The charge pump uses a unique approach
compared to older less–efficient designs.
The charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical
5.5V power supplies. The internal power
supply consists of a regulated dual charge
pump that provides output voltages of
+/-5.5V regardless of input voltage (V_CC)
over the +3.0V to +5.5V range. This
is important to maintain compliant RS-
232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinu-
ous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
output voltages exceed a magnitude of 5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shift-
ing. A description of each phase follows.
Phase 1
— V_SS charge storage — During this phase
of the clock cycle, the positive side of capaci-
tors C₁ and C₂ are initially charged to V_CC.
C_l+ is then switched to GND and the charge
in C_1– is transferred to C_2–. Since C₂₊ is con-
nected to V_CC, the voltage potential across
capacitor C₂ is now 2 times V_CC.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of
C₂ to GND. This transfers a negative gener-
ated voltage to C₃. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the volt-
age to C₃, the positive side of capacitor C₁
is switched to V_CC and the negative side is
connected to GND.
Phase 3
— V_DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C₁ produces –V_CC in
the negative terminal of C₁, which is applied
tCo₂₊thiseanteVg_Ca_Ct,ivtheesvidoeltaogfecappoatecnittoiarlCa_{2c.roSsisncCe2}
is 2 times V_CC.
Phase 4
— V_DD transfer — The fourth phase of
the clock connects the negative terminal
of C₂ to GND, and transfers this positive
generated voltage across C₂ to C₄, the
V_DD storage capacitor. This voltage is
regulated to +5.5V. At this voltage, the in-
ternal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the
positive side of capacitor C₁ is switched to V_CC
and the negative side is switched to GND, al-
lowing the charge pump cycle to begin again.
The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator are present.
Since both V⁺ and V^– are separately gener-
ated
and
from
V^– will
V_CC, in a no–load
be symmetrical.
condition V⁺
Older charge
pump approaches that generate V^– from
V⁺ will show a decrease in the magnitude
of V^– compared to V⁺ due to the inherent
inefficiencies in the design.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • www.exar.com
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SP3221E_102_091014