XRT91L34 Datasheet, PDF (1/38 Pages) Exar Corporation – QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
OCTOBER 2007
REV. 1.0.1
GENERAL DESCRIPTION
The XRT91L34 is a fully integrated quad channel
multirate Clock and Data Recovery (CDR) device for
SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52
Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0
applications. The device provides Clock and Data
Recovery (CDR) function by synchronizing its on-chip
Voltage Controlled Oscillator (VCO) to the incoming
serial data stream. The device internally monitors
Loss of Lock (LOL) conditions and automatically
mutes recovered data upon Loss of Signal (LOS)
conditions.
CLOCK AND DATA RECOVERY OVERVIEW
The clock and data recovery (CDR) unit accepts the
high speed NRZ serial data from the LVDS or
Differential LVPECL receiver and generates a clock
that is the same frequency as the incoming data. The
CDR block uses a reference clock to train and
monitor its clock recovery PLL. All four channels
share a single 77.76MHz or 19.44MHz reference
clock. Upon startup, the PLL locks to the local
reference clock. Once this is achieved, the PLL
FIGURE 1. BLOCK DIAGRAM OF XRT91L34
attempts to lock onto the incoming receive serial data
stream. Whenever the recovered clock frequency
deviates from the local reference clock frequency by
more than approximately ±500 ppm, the clock
recovery PLL will switch and lock back onto the local
reference clock and declare a Loss of Lock.
Whenever a Loss of Lock or a Loss of Signal event
occurs, the CDR will continue to supply a recovered
clock (based on the local reference) to the framer/
mapper device. When the SDEXT is de-asserted by
the optical module or when internal DLOS is
asserted, the receive serial data output will be forced
to a logic zero state for the entire duration that a LOS
condition is declared. This acts as a receive data
mute upon LOS function to prevent random noise
from being misinterpreted as valid incoming data.
When the SDEXT becomes active and the recovered
clock is determined to be within ±500 ppm accuracy
with respect to the local reference source and LOS is
no longer declared, the clock recovery PLL will switch
and lock back onto the incoming receive serial data
stream. Figure 1 shows the block diagram of the
XRT91L34.
RESET
HOST /HW
0
DLOSDIS /SDI
1
INT
CS
SCLK
SDO
DLOSDIS
SDI
Serial Proccesor
Interface
RXDI0P
RXDI0N
LVDS/LVPECL
Input Drivers
100
RXDATAIN
RX LOOP
FILTER
XRT91L34
Global Control Block
CDR
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
CDRDIS0
DATA0RATE1
DATA0RATE0
SDEXT0
POL0
Channel Control Block
DLOSDIS
DLOS
REFCLKP
REFCLKN
TEST
OUTCFG
CDRREFSEL
19.44 / 77.76 MHz
TTLREFCLK
LVDS/LVPECL LEVEL SELECT
RCLKDIS0
LVDS/LVPECL
Output Drivers
RECVD-
DATAOUT ⁰
1
RECVD-
0
CLKOUT
1
HOST MODE
ONLY
RXDO0P
RXDO0N
RXCLKO0P
RXCLKO0N
LOL0
Channel 0
Channel 1
Channel 2
Channel 3
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com