XRT91L30_10 Datasheet, PDF (1/2 Pages) Exar Corporation – STS12-STM4 OR STS3-STM1 SONET-SDH Transceiver

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XRT91L30 STS12-STM4 OR STS3-STM1 SONET-SDH
Transceiver
General Description:
The XRT91L30 is a fully integrated SONET/SDH transceiver for
SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps
STS-3/STM-1 applications. The transceiver includes an on-chip Clock
Multiplier Unit (CMU), which uses a high frequency Phase- Locked
Loop (PLL) to generate the high-speed transmit serial clock from a
slower external clock reference. It also provides Clock and Data
Recovery (CDR) function by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial data stream. The
internal CDR unit can be disabled and bypassed in lieu of an
externally recovered received clock from the optical module. Either
the internally recovered clock or the externally recovered clock can be used for loop timing applications.
The chip provides serial-to-parallel and parallel-to-serial converters using an 8-bit wide LVTTL system
interface in both receive and transmit directions. The transmit section includes an option to accept a parallel
clock signal from the framer/mapper to synchronize the transmit section timing. The device can internally
monitor Loss of Signal (LOS) condition and automatically mute received data upon LOS. An on-chip
SONET/SDH frame byte and boundary detector and frame pulse generator offers the ability recover
SONET/SDH framing and to byte align the receive serial data stream into the 8-bit parallel bus.
Key Features:
 Targeted for SONET STS-12/STS-3 and SDH
STM-4/STM-1 Applications
 Selectable full duplex operation between
STS-12/STM-4 standard rate of 622.08 Mbps
or STS-3/STM-1 155.52 Mbps
 Single-chip fully integrated solution containing
parallel-to-serial converter, clock multiplier unit
(CMU), serialto-parallel converter, clock data
recovery (CDR) functions, and a SONET/SDH
frame and byte boundary detection circuit
 Ability to disable and bypass onchip CDR for external based received reference clock recovery thru
Differential LVPECL input pins XRXCLKIP/N
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