XRT83SL34 Datasheet, PDF (1/80 Pages) Exar Corporation – QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FEBRUARY 2004
REV. P1.0.8
GENERAL DESCRIPTION
The XRT83SL34 is a fully integrated Quad (four
channel) short-haul line interface unit for T1
(1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or 120Ω, or
J1 110Ω applications.
In T1 applications, the XRT83SL34 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements. It
also provides programmable transmit pulse
generators for each channel that can be used for
output pulse shaping allowing performance
improvement over a wide variety of conditions.
The XRT83SL34 provides both a parallel Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit path
with loop bandwidths of less than 3Hz. The
XRT83SL34 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75Ω,
100Ω, 110Ω and 120Ω for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
• T1 Digital Cross-Connects (DSX-1)
• ISDN Primary Rate Interface
• CSU/DSU E1/T1/J1 Interface
• T1/E1/J1 LAN/WAN Routers
• Public switching Systems and PBX Interfaces
• T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL34 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
T P O S _n/T D A T A _n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
R P O S _ n/R D A T A _n
RLOS_n
HW /HOST
W R_R/W
RD_DS
ALE-AS
CS
RDY_DTACK
IN T
MASTER CLOCK SYNTHESIZER
One of four channels, CHANNEL_n - (n= 0:3)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/R X JIT TER
ATTENUATOR
TAOS
ENABLE
T IM IN G
CONTROL
DFM
D R IV E
M O N IT O R
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
D IG ITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/R X JIT TER
ATTENUATOR
T IMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
E Q U A L IZ E R
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
E Q U A L IZ E R
TEST
MICROPROCESSOR CONT ROLLER
MCLKOUT
DMO_n
TTIP_n
T R IN G _n
TXON_n
RTIP_n
RRING_n
ICT
µPTS1
µPTS2
D[7:0]
µPCLK
A[7:0]
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com