XRK799J93 Datasheet, PDF (1/10 Pages) Exar Corporation – INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

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XRK799J93
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
DECEMBER 2006
GENERAL DESCRIPTION
The XRK799J93 is a PLL clock driver designed
specifically for redundant clock tree designs. The
device receives two differential LVPECL clock signals
from which it generates 5 new differential LVPECL
clock outputs. Two of the output pairs regenerate the
input signals frequency and phase while the other
three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero
delay buffer performance.
The XRK799J93 Intelligent Dynamic Clock Switch
circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW
for at least 1 period), the INP_BAD for that CLK will
REV. 1.0.1
be latched (H). If that CLK is the primary clock, the
device will switch to the good secondary clock and
phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump
caused by a failed clock is eliminated.
FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK799J93
CLK ^_Selected
INP1Bad
INP0Bad
Dynamic
Man_Override
Alarm_Reset
Switch
Logic
Qb0
Qb0
Sel_CLK
Qb1
Qb1
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
PLL_En
Qb2
÷2
Qb2
PLL
÷4
Qa0
Qa0
160-380MHz
Qa1
Qa1
MR
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com