XR16M890 Datasheet, PDF (1/2 Pages) Exar Corporation – Single-Channel UARTs with Selectable Bus Interfaces

8-bit (Intel/Motorola/VLIO) UART with 128-Byte FIFO and Integrated Level Shifters
XR16M890
Single-Channel UARTs with Selectable Bus Interfaces
Simplify Mixed Voltage Designs for Next Generation Systems
The XR16M890¹ (M890) is a single-channel Universal Asynchronous Receiver
and Transmitter (UART) with integrated level shifters and 128 bytes of transmit
and receive FIFOs.
For flexibility in a mixed voltage environment, the M890 has 4 VCC pins. There
is a VCC pin for the core, a VCC pin for the UART signals, a VCC pin for the
CPU interface signals and a VCC pin for the GPIO signals. The VCC pins for the
UART, GPIO and CPU interface signals allow for the M890 to interface with
devices operating at different voltage levels eliminating the need for external
voltage level shifters. The VCC core voltage helps to lower the overall power
consumption for applications that use slower data rates.
The Auto RS-485 Half-Duplex Direction control feature simplifies both the
hardware and software for half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection and Address Byte Control features
increase the performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator feature allows the transmitter
and receiver to operate at different baud rates. In addition, the Fractional Baud
Rate Generator feature provides flexibility for crystal/clock frequencies for
generating standard and non-standard baud rates.
The M890 has programmable transmit and receive FIFO trigger levels, automatic
hardware and software flow control, and data rates of up to 24 Mbps. Power
consumption of the M890 can be minimized by enabling the sleep mode.
The M890 has a 16550 compatible register set that provide users with operating
status and control, receiver error indications, and modem serial interface
controls. An internal loopback capability allows onboard diagnostics. The M890
has a selectable Intel/Motorola/VLIO bus interface.
NOTE: ¹Covered by U.S. Patent #5,649,122.
FEATURES
• Integrated Level Shifters on
CPU interface, UART and
GPIO signals
• Intel/Motorola/VLIO Bus
Interface select
• 24 Mbps maximum UART data
rate
• Up to 16 GPIOs
• 128-Bytes TX and RX FIFOs
• Programmable TX/RX trigger
levels
• TX/RX FIFO Level Counters
• Independent TX/RX Baud Rate
Generator
• Fractional Baud Rate Generator
• Auto RTS/CTS Hardware Flow
Control
• Auto XON/XOFF Software Flow
Control
• Auto RS-485 Half-Duplex
Direction Control
• Multidrop mode w/ Auto
Address Detect (RX)
• Multidrop mode w/ Address
Byte Control (TX)
• Sleep Mode with Automatic
Wake-up
• Infrared (IrDA 1.0 and 1.1)
mode
• 1.62V to 3.63V supply operation
• Crystal oscillator or external
clock input
• 5V tolerant inputs
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