TAN-014 Datasheet, PDF (1/10 Pages) Exar Corporation – A Comparison between Exar’s XR-88C681

TAN - 014
A Comparison between Exar’s XR-88C681 with Signetics’ SC26C92 DUART Devices
Comparison of EXAR DUART (XR-88C681 device) with that of
Signetics (SC26C92)
Introduction
Although the XR-88C681 and the Signetics SC26C92 devices have exactly the same pin
outs, they are not drop-in compatible devices. There are three minor hardware difference,
and numerous software/firmware related differences between these two devices.
Hardware Difference:
1. The XR-88C681 device uses 3 byte FIFOs in the Transmitter and Receiver of both
channels; whereas the SC26C92 device uses 8 byte FIFOs. Of course this Hardware
difference also results in differences in the DUART Interrupt Structure for the Transmit
and Receiver FIFO, as will be presented below.
2. The SC26C92 has an additional Mode Register, MR0n, for each channel.
3. The SC26C92 does not come in a 28 pin DIP
Firmware/Software Related Differences:
The Register Addressing is slightly different between these two devices. As well as the
meaning of commands written to the Command Registers. The specifics of these
differences are enumerated in this write up in Tables 1 through 3. The are numerous other
differences in the feature being offered by each of the devices. These differences are also
listed below..
1. I/Z Modes - XR-88C681
The XR-88C681 (in 40 pin DIP or 44 pin PLCC package) may be programmed to operate
in two modes to accommodate different CPU interface requirements. This feature is not
available in the 28 pin DIP packaged devices. In the I-mode (or Intel Mode), which is the
default mode after a hardware reset, interrupt prioritization and interrupt vector
generation, if required are implemented using external hardware. In this mode, the on-
chip interrupt vector register (IVR) is not used, and is available for use as an auxiliary
read/write register for any purpose. The Signetics SC26C92 device only operates in the I
mode. In the Z (or Zilog) mode, which is invoked via a command to Command Register
B, pins 37, 38, and 39 are designated interrupt acknowledge input (IACKN), interrupt
enable output (IEO) and interrupt enable input (IEI), respectively. IEI and IEO are the
input and output of an interrupt daisy chain, as illustrated in Figure 1 on the XR-88C681
data sheet. A logic high at the IEI input allow the DUART to generate an interrupt
request. A device with its IEI input “high” which is requesting an interrupt sets its IEO
output low to inhibit lower priority devices from generating their own interrupt requests.