MP1230A Datasheet, PDF (1/12 Pages) Exar Corporation – CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter

FEATURES
• Superior Ruggedized 1230 Series: 2 KV ESD
• Four Quadrant Multiplication
• Stable, More Accurate Segmented DAC Approach
– 0.2 ppm/°C Linearity Tempco
– 2 ppm/°C Max Gain Error Tempco
– Lowest Sensitivity to Amplifier Offset
– Lowest Output Capacitance (C_OUT = 80pF)
– Lower Glitch Energy
• Monotonic over Temperature Range
MP1230A/31A/32A
CMOS Microprocessor Compatible
Double-Buffered 12-Bit
Digital-to-Analog Converter
• Lower Data Bus Feedthrough @ CS = 1
• V_DD from +11 V to +16 V
• Latch-Up Free CMOS Technology
• 12-Bit Bus Version: MP1208/1209/1210
• 16-Bit Upgrade: MP7636A
GENERAL DESCRIPTION
The MP1230A series are superior pin for pin replacements
for the 1230 series. The MP1230A series is manufactured using
advanced thin film resistors on a double metal CMOS process
which promotes significant improvements in reliability, latch-up
free performance and ESD protection.
The MP1230A series incorporates a unique decoding tech-
nique yielding lower glitch, higher speed and excellent accuracy
over temperature and time. 12-bit linearity is achieved without
trimming. Outstanding features include:
– Stability: integral and differential linearity tempcos are rated
at 0.2 ppm/°C typical. Monotonicity is guaranteed over all
temperature ranges. Scale factor tempco is a low 2 ppm/°C
maximum.
– Low Output Capacitance: Due to smaller MOSFET switch
geometries allowed by decoding, the output capacitance at
I_OUT1 and I_OUT2 is a low 80pF / 40pF and 25pF / 65 pF. This
less than half the competitive DAC 1230 series. Lower ca-
pacitance allows the MP1230A series to achieve settling
times faster than 1 µs for a 10 V step.
– Low Sensitivity to Output Amplifier Offset: The linearity er-
ror caused by amplifier offset is reduced by a factor of 2 in the
MP1230A series over conventional R-2R DACs.
The MP1230A series uses a circuit which reduces transients
in the supplies caused by DATA bus transitions at CS = 1.
SIMPLIFIED BLOCK DIAGRAM
V_DD
V_REF
DB11-DB4
DB3-DB0
8
BYTE1/BYTE2
INPUT LATCH DAC LATCH
D
Q
DQ
8
LE
8 12
LE
V_REF
R_FB
I_OUT1
I_OUT2
CS
WR1
D
Q
12
4
4
LE
XFER WR2 DGND
AGND
Rev. 2.00
1