DAN-144 Datasheet, PDF (1/3 Pages) Exar Corporation – EXAR’S XR16L784 COMPARED

DATA COMMUNICATIONS APPLICATION NOTE
DAN144
August 2002
EXAR’S XR16L784 COMPARED WITH OXFORD’S OX16C954
Author: PY
1.0 INTRODUCTION
This application note describes the hardware and firmware-related differences between Exar’s XR16L784 with
Oxford’s OX16C954. The Exar and Oxford Quad UARTs are very different devices.
1.1 HARDWARE DIFFERENCES
• The XR16L784 is available in the smaller 64-pin TQFP package, while the OX16C954 is available in the 68-
pin PLCC and 80-pin TQFP packages.
• Overall, the XR16L784 is simpler and more flexible to design with these three features:
• The XR16L784 can operate from 2.95 to 5.5 V with 5 V tolerant inputs. The OX16C954 can operate at 5 V
or 3.3 V, but it does not have 5 V tolerant inputs at 3.3 V operation.
• The XR16L784 has a single chip select input pin and interrupt output pin for all 4 channels while the
OX16C954 has individual chip select input pin and interrupt output pin for each channel.
• The XR16L784 has a 16/68# input pin to select the device for Intel or Motorola data bus interface. The
OX16C954 can operate only in the Intel data bus interface.
1.2 FIRMWARE DIFFERENCES
• The internal registers of the XR16L784 are much simpler than the internal registers of the OX16PCI954. The
XR16L784 has a flat sequential register set while the OX16PCI954 has 3 levels of shadow registers. The
XR16L784 uses 4 address lines to access the internal registers instead of the traditional 3 address lines
therefore eliminating having to deal with shadow registers. The 16C550 Standard Register Set and the
Enhanced Register Set can all be accessed from the same location. Note that the XR16L784 has more reg-
isters in the Enhanced Register Set than the OX16C954 has in its Enhanced Register Set. The OX16C954
has a Standard Register Set, Enhanced Register Set, Indexed Control Register Set and Additional Status
Register Set. As long as the last value written to LCR was not 0xBF, the Index Control Register (ICR) is
accessed by writing the desired address offset for the ICR to the Scratchpad register and then writing to the
ICR. Note that this is for writing to the ICR only. To read from ICR, you must write to a bit in one of the
Indexed Control Registers to enable reading from the ICR. The Additional Status Registers can only be read
when another bit in the Indexed Control Registers is set.
• The XR16L784 has the ability to write to all channels simultaneously (via Device Configuration Register
REG2 bit-0) for smaller and quicker initialization routines. Once simultaneous write has been enabled for the
XR16L784, writing to any channel register will write to the same register of all channels. In the OX16C954, it
is necessary to initialize each channel individually.
• The interrupt scheme of the XR16L784 and OX16C954 is similar to the interrupt scheme used in the industry
standard 16C550 but the XR16L784 has some enhancements like the ability to clear one interrupt in each of
the channels per interrupt service by reading the Global Interrupt Status Registers. The OX16C954 can only
service one channel per interrupt service.
• In addition to Automatic RTS/CTS Hardware Flow Control, the XR16L784 also supports Automatic DTR/
DSR Hardware Flow Control. This gives hardware designers flexibility in selecting which signals to use for
hardware flow control. This feature is not available in the OX16C954.
• The XR16L784 has Automatic 2 character Xon/Xoff Software Flow Control. In Automatic 2 character Xon/
Xoff Software Flow Control, two flow control characters (Xoff1, Xoff2, Xon1, Xon2) are sent at the appropri-
ate times instead of just a single character. This is to ensure that the first character is not accidentally inter-
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