DAN-143 Datasheet, PDF (1/3 Pages) Exar Corporation – EXAR’S XR17C154 COMPARED

DATA COMMUNICATIONS APPLICATION NOTE
DAN143
August 2002
EXAR’S XR17C154 COMPARED WITH OXFORD’S OX16PCI954
Author: PY
1.0 INTRODUCTION
This application note describes the major hardware and firmware differences between Exar’s XR17C154 and
Oxford’s OX16PCI954.
1.1 HARDWARE DIFFERENCES
• The XR17C154 is available in a smaller 144-pin TQFP package than the OX16PCI954 which is available in a
160-pin TQFP package. They are not available in the same packages therefore they are not pin-to-pin com-
patible. The XR17C154 is pin-to-pin and software compatible with the XR17C158 in case there is ever a
need to migrate to the PCI Octal UART.
• The XR17C154 is specifically a PCI Quad UART. The OX16PCI954 is a PCI Quad UART with a parallel port.
1.2 FIRMWARE DIFFERENCES
• The internal registers of the XR17C154 are much simpler than the internal registers of the OX16PCI954.
The XR17C154 has a flat sequential register set while the OX16PCI954 has 3 levels of shadow registers.
The XR17C154 uses 4 address lines to access the internal registers instead of the traditional 3 address lines
therefore eliminating having to deal with shadow registers. The 16C550 Standard Register Set and the
Enhanced Register Set can all be accessed from the same location. Note that the XR17C154 has more reg-
isters in the Enhanced Register Set than the OX16PCI954 has in its Enhanced Register Set. The
OX16PCI954 has a Standard Register Set, Enhanced Register Set, Indexed Control Register Set and Addi-
tional Status Register Set. As long as the last value written to LCR was not 0xBF, the Index Control Register
(ICR) is accessed by writing the desired address offset for the ICR to the Scratchpad register and then writ-
ing to the ICR. Note that this is for writing to the ICR only. To read from ICR, you must write to a bit in one of
the Indexed Control Registers to enable reading from the ICR. The Additional Status Registers can only be
read when another bit in the Indexed Control Registers is set.
• The XR17C154 has the ability to write to all channels simultaneously (via Device Configuration Register
REGB bit-0) for smaller and quicker initialization routines. Once simultaneous write has been enabled for
the XR17C154, writing to any channel register will write to the same register of all channels. In the
OX16PCI954, it is necessary to initialize each channel individually.
• The XR17C154 can perform DWORD (4 bytes) reads from the RX FIFO therefore unloading up to 4 bytes
per read cycle from the RX FIFO. The same concept applies when performing DWORD writes to the TX
FIFO. Up to 4 bytes can be loaded per write cycle into the TX FIFO. The OX16PCI954 can only read or
write one byte at a time, hence a lower throughput.
• The XR17C154 supports Burst Read and Burst Write PCI bus transactions (refer to PCI Local Bus Specifica-
tions Revision 2.2). In Burst Read Mode, the XR17C154 can unload up to 64 bytes from the RX FIFO in a
single PCI bus transaction. In Burst Write Mode, the XR17C154 can load up to 64 bytes into the TX FIFO in
a single PCI bus transaction. The OX16PCI954 does not support burst read or burst write and any attempt
to burst will be terminated with Disconnect with Data. It is only capable of unloading one data byte from the
RX FIFO and loading one data byte to the TX FIFO per transaction.
• The XR17C154 has Automatic 1 or 2 character Xon/Xoff Software Flow Control. In the Automatic 1 charac-
ter Xon/Xoff Software Flow Control, an Xoff will be sent to the remote transmitter when the local RX FIFO
reaches the trigger level to halt remote data transmission and an Xon will be sent when the FIFO falls below
the the trigger level to resume data transmission. In Automatic 2 character Xon/Xoff Software Flow Control,
two Xoff and Xon characters are sent at the appropriate times instead of just a single character. This is to
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