DAN-135 Datasheet, PDF (1/2 Pages) Exar Corporation – EXAR XR16L580 COMPARED

DATA COMMUNICATIONS APPLICATION NOTE
DAN135
EXAR’S XR16L784 COMPARED WITH TI’S TL16C754B
June 2002
Author: PY
1.0 INTRODUCTION
This application note describes the hardware and firmware-related differences between Exar’s XR16L784 with
TI’s TL16C754B. The Exar and TI QUARTs are very different devices.
1.1 HARDWARE DIFFERENCES
• The XR16L784 is available in the smaller 64-pin TQFP package, while the TL16C754B is available in the 68-
pin PLCC and 80-pin PQFP packages.
• The XR16L784 can operate at either 5 V or 3.3 V with 5 V tolerant inputs. The TL16C754B can operate at 5
V or 3.3 V, but it does not have 5 V tolerant inputs at 3.3 V.
• The XR16L784 has a single chip select input pin and interrupt output pin for all 4 channels while the
TL16C754B has a chip select input pin and interrupt output pin for each channel.
• The XR16L784 has a 16/68# input pin to select the device for Intel or Motorola data bus interface. The
TL16C754B can operate in the Intel data bus interface.
1.2 FIRMWARE DIFFERENCES
• The first 8 registers and the baud rate divisors of both the XR16L784 and TL16C754B are similar to the
industry standard 16C550 register set. The enhanced registers of the XR16L784 can be accessed sequen-
tially after the 16C550 registers, but the TL16C754B requires setting the Line Control Register (LCR) to
0xBF before accessing the enhanced registers.
• The XR16L784 has the ability to write to all channels simultaneously for smaller and quicker initialization rou-
tines. Once simultaneous write has been enabled for the XR16L784, writing to any channel register will write
to the same register of all channels. In the TL16C754B, it is necessary to initialize each channel individually.
• The interrupt scheme of the XR16L784 and TL16C754B is similar to the interrupt scheme used in the indus-
try standard 16C550 but the XR16L784 has some enhancements like the ability to clear an interrupt in all
channels per interrupt service by reading the Global Interrupt Status Registers. The TL16C754B can only
service one channel per interrupt.
• The XR16L784 has programmable FIFO Trigger Levels of 1 through 64 to optimize the performance for each
individual application. The TL16C754B only has 4 Selectable Trigger Levels.
• In addition to Automatic RTS/CTS Hardware Flow Control, the XR16L784 also supports Automatic DTR/
DSR Hardware Flow Control. This gives hardware designers flexibility in selecting which signals to use for
hardware flow control. This feature is not available in the TL16C754B.
• The XR16L784 has Automatic 1 or 2 character Xon/Xoff Software Flow Control. In the Automatic 1 character
Xon/Xoff Software Flow Control, an Xoff will be sent to the remote transmitter when the local RX FIFO
reaches the trigger level to halt remote data transmission and an Xon will be sent when the FIFO falls below
the the trigger level to resume data transmission. In Automatic 2 character Xon/Xoff Software Flow Control,
two Xoff and Xon characters are sent at the appropriate times instead of just a single character. This is to
ensure that the first character is not accidentally interpreted as a software flow control character if it was not
meant to be. The Automatic 2 Character Flow Control provides a much more reliable mechanism. The
TL16C754B only has the Automatic 1 character Xon/Xoff Software Flow Control.
• The XR16L784 has an Automatic RS485 Half-Duplex Control that will automatically control the direction of
the RS485 transceivers. When data is loaded into the FIFO, the RTS# pin will become a logic 1 for transmit
and when it is done transmitting all of the characters in the FIFO, it will change to a logic 0 so that it can start
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