DAN-120 Datasheet, PDF (1/3 Pages) Exar Corporation – EXAR’S XR68C92/192 AND XR88C92/192 COMPARED

DATA COMMUNICATIONS APPLICATION NOTE
DAN120
June 2002
EXAR’S XR68C92/192 AND XR88C92/192 COMPARED WITH PHILIP’S SC28L92
Author: PY
1.0 INTRODUCTION
This application note describes the major difference between Exar’s XR68C92/192 and XR88C92/192 with
Philips’s SC28L92. These devices are very similar, with a few hardware, firmware-related and bus timing dif-
ferences.
1.1 HARDWARE DIFFERENCES
• The Philips SC28L92 is available in two footprints: 44-pin PLCC and 44-pin QFP. The XR68C92/192 and
XR88C92/192 are available in these footprints as well as in a 40-pin PDIP.
• In the PLCC and QFP packages, the Exar and Philips DUARTs are pin-to-pin compatible with one exception.
The Philips SC28L92 has an additional pin I/M which is not available in the XR68C92/192 and XR88C92/192
(the corresponding pin is a no-connection). If the I/M pin in the SC28L82 is grounded (Motorola Mode), then
it will be functionally compatible with the XR68C92/192 and if the I/M pin is tied to VCC (Intel Mode) then it
will be functionally compatible with the XR88C92/192.
• The Exar’s 44-pin TQFP package is the same size and has the same pitch as the Philips’ 44-pin QFP pack-
age. But they differ in the package thickness and the lead length. See the list below:
Thickness:
Exar
1.4mm
Philips
1.75mm
Lead Length, Lp:
0.45mm < Lp < 0.75mm
0.55mm < Lp < 0.95mm
• It is to be noted that the XR68C92/192 or the XR88C92/192 can replace the SC28L92 without any hardware
changes.
1.2 FIRMWARE DIFFERENCES
All the internal registers in the SC28L92, XR68C92/192 and XR88C92/192 are identical with only a few excep-
tions:
• The MR0 register bit-3 in SC28L92 needs to be a logic 0 (8 byte FIFO) to be functionally compatible with the
XR68C92 and the XR88C92. The MR0 register bit-3 in SC28L92 needs to be a logic 1 (16 byte FIFO) to be
functionally compatible with the XR68C192 and the XR88C192. MR0 register bit-3 is unused in the
XR68C92/192 and XR88C92/192.
• The unique feature of the Exar DUARTs is that in the multi-drop mode, the user need not wait at all in order
to change A/D tag from address to data. This allows the user to possibly load the entire polling packet data
to the TX FIFO.
• When MR0 register bit-6 is a logic 0 and MR1register bit-6 is a logic 1, the Receive FIFO Trigger level in the
XR68C92/192 and XR88C92/192 is 6 but with the same bits set to those values in the SC28L92, the Receive
FIFO Trigger level is 8. In most cases, this difference will not have any noticeable effect during normal oper-
ation. There is no similar difference for the Transmit FIFO Trigger Levels.
1.3 BUS TIMING DIFFERENCES
• The XR68C92/192 and XR88C92/192 data access time is shorter than the SC28L92. The data access time
during a read is a maximum of 32 ns for the Exar DUARTs, whereas it is a maximum of 55 ns for the
SC28L92.
EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com • [e-mail]