PLR135 Datasheet, PDF (8/8 Pages) Everlight Electronics Co., Ltd – Technical Data Sheet Photo link Light Receiver Unit

PLR135
Application Notes: PLR135 Series PCB layout for motherboard integration
To achieve better jitter and low input optical power performances, several PCB layout
guidelines must be followed. These guidelines ensure the most reliable PLR135 POF performance
for the motherboard integration. Failed to implement these PCB guidelines may affect the PLR135
jitter and low input power performances.
1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size
805 or smaller) capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf
act as a low impedance path to ground for any stray high frequency transient noises.
2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance
formed by an isolated Vcc and Gnd planes is critical. The POF device must be mounted directly
on these two planes to reduce the lead parasitic inductance.
3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at
a single point using ferrite beads. The beads are used to block the high frequency noises from
the digital planes while still allowing the DC connections between the planes
EVERLIGHT ELECTRONICS CO., LTD.
Office: No 25, Lane 76, Sec 3, Chung Yang Rd,
Tucheng, Taipei 236, Taiwan, R.O.C
Tel: [phone]
Fax: [phone]
http://www.everlight.com
Everlight Electronics Co., Ltd.
Device NO.: DPL-135-001
http://www.everlight.com
Prepared date: 07-25-2005
Rev 2
Page: 8 of 8
Prepared By: Chin-Chia Hsu