EUA6021A Datasheet, PDF (12/16 Pages) Eutech Microelectronics Inc – 2.5-W Stereo Audio Power Amplifier with Advanced DC Volume Control

EUA6021A
Application Information
VOLUME Operation
The VOLUME pin controls the BTL volume when driving
speakers, and the SE volume when driving headphones.
This pin is controlled with a dc voltage, which should not
exceed V_DD.
The output volume increases in discrete steps as the dc
voltage increases and decreases in discrete steps as the dc
voltage decreases. There are a total of 32 discrete gain steps
of the amplifier and range from -85 dB to 20 dB for BTL
operation and -85 dB to 14 dB for SE operation.
A pictorial representation of the typical volume control can
be found in Figure 26.
Figure 26. Typical DC Volume Control Operation
Shutdown Modes
The EUA6021A employs a shutdown mode of operation
designed to reduce supply current, I_DD, to the absolute
minimum level during periods of nonuse for
battery-power conservation. The SHUTDOWN input
terminal should be held high during normal operation
when the amplifier is in use. Pulling SHUTDOWN low
causes the outputs to mute and the amplifier to enter a
low-current state, I_DD=20µA. SHUTDOWN should never
be left unconnected because amplifier operation would be
unpredictable.
Table 1 . SE/BTL , and Shutdown Function
Inputs
Amplifier State
SE/BTL SHUTDOWN _{INPUT OUTPUT}
X
Low
High
Low
High
Low
High
High
High
High
X= Do not care
X
Mute
Line
BTL
Line
SE
HP
BTL
HP
SE
FADEOperation
For design flexibility, a fade mode is provided to slowly
ramp up the amplifier gain when coming out of shutdown
mode and conversely ramp the gain down when going into
shutdown. This mode provides a smooth transition
between the active and shutdown states and virtually
eliminates any pops or clicks on the outputs.
When the ^FADEinput is a logic low, the device is placed
into fade-on mode. A logic high on this pin places the
amplifier in the fade-off mode. The voltage trip levels for
a logic low (V_IL) or logic high (V_IH) can be found in the
recommended operating conditions table.
When a logic low is applied to the ^FADE pin and a logic
low is then applied on the ^SHUTDOWNpin, the channel
gain steps down from gain step to gain step at a rate of
two clock cycles per step. With a nominal internal clock
frequency of 58HZ,this equates to 34 ms (1/24 Hz) per
step. The gain steps down until the lowest gain step is
reached .The time it takes to reach this step depends on the
gain setting prior to placing the device in shutdown. For
example, if the amplifier is in the highest gain mode of
20dB, the time it takes to ramp down the channel gain is
1.05 seconds. This number is calculated by taking the
number of steps to reach the lowest gain from the highest
gain, or 31 steps , and multiplying by the time per step, or
34 ms.
After the channel gain is stepped down to the lowest gain,
the amplifier begins discharging the bypass capacitor from
the nominal voltage of V_DD/2 to ground.
This time is dependent on the value of the bypass
capacitor. For a 0.47-µF capacitor that is used in the
application diagram in Figure 1, the time is approximately
500ms. This time scales linearly with the value of bypass
capacitor. For example, if a 1-µF capacitor is used for
bypass, the time period to discharge the capacitor to
ground is twice that of the 0.47-µF capacitor, or 1 second.
DS6021A Ver 1.2 Jun. 2007
12