TTW3C115N16 Datasheet, PDF (1/10 Pages) eupec GmbH – Phase Control Thyristor Module

Technische Information / Technical Information
Netz-Thyristor-Modul
Phase Control Thyristor Module
TT W3C 115 N 16
(ISOPACK)
N
W3
Elektrische Eigenschaften / Electrical properties
Höchstzulässige Werte / Maximum rated values
Datenblatt gilt auch für TDW3H115N16
Datasheet also valid for TDW3H115N16
Periodische Vorwärts- und Rückwärts-Spitzensperrspannung Tvj = - 40°C...Tvj max
repetitive peak forward off-state and reverse voltages
V_DRM, V_RRM
1600 V
Vorwärts-Stoßspitzensperrspannung
non-repetitive peak forward off-state voltage
T_vj = - 40°C...T_{vj max}
V_DSM
1600 V
V
Rückwärts-Stoßspitzensperrspannung
non-repetitive peak reverse voltage
T_vj = + 25°C...T_{vj max}
V_RSM
1700 V
Durchlaßstrom-Grenzeffektivwert (pro Element)
RMS on-state current (per chip)
I_TRMSM
100 A
Effektivstrom (pro Phase)
RMS current (per arm)
T_C = 85°C
T_C = 73°C
T_A = 45°C, KM 11
T_A = 45°C, KM 33
T_A = 35°C, KM 14 (V_L = 45l/s)
T_A = 35°C, KM 33 (V_L = 90l/s)
I_RMS
115 A
141 A
38 A
55 A
97 A
115 A
Stoßstrom-Grenzwert
surge current
T_vj = 25°C, t_p = 10ms
T_vj = T_{vj max}, t_p = 10ms
I_TSM
1000 A
870 A
Grenzlastintegral
I²t-value
T_vj = 25°C, t_p = 10ms
I²t
T_vj = T_{vj max}, t_p = 10ms
5000 A²s
3780 A²s
Kritische Stromsteilheit
critical rate of rise of on-state current
DIN IEC 747-6
(di/dt)_cr
f = 50Hz, i_GM = 0,6A, di_G/dt = 0,6A/µs
120 A/µs
Kritische Spannungssteilheit
critical rate of rise of off-state voltage
T_vj = T_{vj max}, v_D = 0,67 V_DRM
8. Kennbuchstabe / 8th letter F
(dv/dt)_cr
1000 V/µs
Charakteristische Werte / Characteristic values
Durchlaßspannung
on-state voltage
Schleusenspannung
threshold voltage
Ersatzwiderstand
slope resistance
Zündstrom
gate trigger current
Zündspannung
gate trigger voltage
Nicht zündender Steuerstrom
gate non-trigger current
Nicht zündende Steuerspannung
gate non-trigger voltage
Haltestrom
holding current
Einraststrom
latching current
Vorwärts- und Rückwärts-Sperrstrom
forward off-state and reverse currents
Zündverzug
gate controlled delay time
T_vj = T_{vj max}, i_T = 150A
v_T
T_vj = T_{vj max}
V_(T0)
T_vj =T_{vj max}
r_T
T_vj = 25°C, v_D = 6V
I_GT
T_vj = 25°C, v_D = 6V
V_GT
T_vj = T_{vj max}, v_D = 6V
T_vj = T_{vj max}, v_D = 0,5 V_DRM
T_vj = T_{vj max}, v_D = 0,5 V_DRM
I_GD
V_GD
T_vj = 25°C, v_D = 6V, R_A = 5Ω
I_H
T_vj = 25°C, v_D = 6V, R_GK ≥ 20Ω
I_L
i_GM = 0,6A, di_G/dt = 0,6A/µs, t _g = 10µs
T_vj = T_{vj max}
v_D = V_DRM, v_R = V_RRM
i_D, i_R
DIN IEC 747-6
t_gd
T_vj = 25°C, i_GM = 0,6A, di_G/dt = 0,6A/µs
max. 1,81 V
0,95 V
4,3 mΩ
max. 150 mA
max. 2,5 V
max. 5,0 mA
max. 2,5 mA
max. 0,2 V
max. 200 mA
max. 600 mA
max. 10 mA
max. 1,2 µs
BIP PPE 4 rev.2
25. Okt 05
A 11/05
Seite/page 1(9)